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2017-07-17target/arm: use DISAS_EXIT for eret handlingAlex Bennée
Previously DISAS_JUMP did ensure this but with the optimisation of 8a6b28c7 (optimize indirect branches) we might not leave the loop. This means if any pending interrupts are cleared by changing IRQ flags we might never get around to servicing them. You usually notice this by seeing the lookup_tb_ptr() helper gainfully chaining TBs together while cpu->interrupt_request remains high and the exit_request has not been set. This breaks amongst other things the OPTEE test suite which executes an eret from the secure world after a non-secure world IRQ has gone pending which then never gets serviced. Instead of using the previously implied semantics of DISAS_JUMP we use DISAS_EXIT which will always exit the run-loop. CC: Etienne Carriere <etienne.carriere@linaro.org> CC: Joakim Bech <joakim.bech@linaro.org> CC: Jaroslaw Pelczar <j.pelczar@samsung.com> CC: Peter Maydell <peter.maydell@linaro.org> CC: Emilio G. Cota <cota@braap.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm: use gen_goto_tb for ISB handlingAlex Bennée
While an ISB will ensure any raised IRQs happen on the next instruction it doesn't cause any to get raised by itself. We can therefore use a simple tb exit for ISB instructions and rely on the exit_request check at the top of each TB to deal with exiting if needed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-6-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm/translate: ensure gen_goto_tb sets exit flagsAlex Bennée
As the gen_goto_tb function can do both static and dynamic jumps it should also set the is_jmp field. This matches the behaviour of the a64 code. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-5-alex.bennee@linaro.org [tweak to multiline comment formatting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm/translate.h: expand comment on DISAS_EXITAlex Bennée
We already have an exit condition, DISAS_UPDATE which will exit the run-loop. Expand on the difference with DISAS_EXIT in the comments. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-4-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm/translate: make DISAS_UPDATE match declared semanticsAlex Bennée
DISAS_UPDATE should be used when the wider CPU state other than just the PC has been updated and we should therefore exit the TCG runtime and return to the main execution loop rather assuming DISAS_JUMP would do that. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-3-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17target/arm: Make Cortex-M3 and M4 default to 8 PMSA regionsPeter Maydell
The Cortex-M3 and M4 CPUs always have 8 PMSA MPU regions (this isn't a configurable option for the hardware). Make the default value of the pmsav7-dregion property be set per-cpu, so we don't need to have every user of these CPUs set it manually. (The existing default of 16 is correct for the other PMSAv7 core, the Cortex-R5.) This fixes a bug where we were creating the M3 and M4 with too many regions; most guest software would not notice or care, though, since it would just not use the registers associated with the unexpected extra regions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 1499788408-10096-4-git-send-email-peter.maydell@linaro.org
2017-07-14Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20170714' into ↵Peter Maydell
staging s390x/kvm/migration/cpumodel: fixes, enhancements and cleanups - add a network boot rom for s390 (Thomas Huth) - migration of storage attributes like the CMMA used/unused state - PCI related enhancements - full support for aen, ais and zpci - migration support for css with vmstates (Halil Pasic) - cpu model enhancements for cpu features - guarded storage support # gpg: Signature made Fri 14 Jul 2017 11:33:04 BST # gpg: using RSA key 0x117BBC80B5A61C7C # gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>" # Primary key fingerprint: F922 9381 A334 08F9 DBAB FBCA 117B BC80 B5A6 1C7C * remotes/borntraeger/tags/s390x-20170714: (40 commits) s390x/gdb: add gs registers s390x/arch_dump: also dump guarded storage control block s390x/kvm: enable guarded storage s390x/kvm: Enable KSS facility for nested virtualization s390x/cpumodel: add esop/esop2 to z12 model s390x/cpumodel: we are always in zarchitecture mode s390x/cpumodel: wire up new hardware features s390x/flic: migrate ais states s390x/cpumodel: add zpci, aen and ais facilities s390x: initialize cpu firstly pc-bios/s390: rebuild s390-ccw.img pc-bios/s390: add s390-netboot.img pc-bios/s390-ccw: Link libnet into the netboot image and do the TFTP load pc-bios/s390-ccw: Add virtio-net driver code pc-bios/s390-ccw: Add core files for the network bootloading program roms/SLOF: Update submodule to latest status pc-bios/s390-ccw: Add code for virtio feature negotiation pc-bios/s390-ccw: Remove unused structs from virtio.h pc-bios/s390-ccw: Move byteswap functions to a separate header pc-bios/s390-ccw: Add a write() function for stdio ... Conflicts: target/s390x/kvm.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-14Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* gdbstub fixes (Alex) * IOMMU MemoryRegion subclass (Alexey) * Chardev hotswap (Anton) * NBD_OPT_GO support (Eric) * Misc bugfixes * DEFINE_PROP_LINK (minus the ARM patches - Fam) * MAINTAINERS updates (Philippe) # gpg: Signature made Fri 14 Jul 2017 11:06:27 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (55 commits) spapr_rng: Convert to DEFINE_PROP_LINK cpu: Convert to DEFINE_PROP_LINK mips_cmgcr: Convert to DEFINE_PROP_LINK ivshmem: Convert to DEFINE_PROP_LINK dimm: Convert to DEFINE_PROP_LINK virtio-crypto: Convert to DEFINE_PROP_LINK virtio-rng: Convert to DEFINE_PROP_LINK virtio-scsi: Convert to DEFINE_PROP_LINK virtio-blk: Convert to DEFINE_PROP_LINK qdev: Add const qualifier to PropertyInfo definitions qmp: Use ObjectProperty.type if present qdev: Introduce DEFINE_PROP_LINK qdev: Introduce PropertyInfo.create qom: enforce readonly nature of link's check callback translate-all: remove redundant !tcg_enabled check in dump_exec_info vl: fix breakage of -tb-size nbd: Implement NBD_INFO_BLOCK_SIZE on client nbd: Implement NBD_INFO_BLOCK_SIZE on server nbd: Implement NBD_OPT_GO on client nbd: Implement NBD_OPT_GO on server ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-14s390x/gdb: add gs registersChristian Borntraeger
Let's provide the guarded storage registers via gdb server. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-14s390x/arch_dump: also dump guarded storage control blockChristian Borntraeger
Write the new note section of type 30b (guarded storage control block). Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-14s390x/kvm: enable guarded storageFan Zhang
Introduce guarded storage support for KVM guests on s390. We need to enable the capability, extend machine check validity, sigp store-additional-status-at-address, and migration. The feature is fenced for older machine type versions. Signed-off-by: Fan Zhang <zhangfan@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-14s390x/kvm: Enable KSS facility for nested virtualizationFarhan Ali
If the host supports keyless subset (KSS) then first level guest (G2) should enable KSS facility as well. Signed-off-by: Farhan Ali <alifm@linux.vnet.ibm.com> Reviewed-by: Eric Farman <farman@linux.vnet.ibm.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-14s390x/cpumodel: add esop/esop2 to z12 modelJason J. Herne
Add esop and esop2 features to z12 model where esop2 was originally introduced. Disable esop and esop2 when using compatibility machine v2.9 or earlier. Signed-off-by: Jason J. Herne <jjherne@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-14s390x/cpumodel: we are always in zarchitecture modeJason J. Herne
In QEMU, a guest VCPU always started in and never was able to leave z/Architecture mode. Now we have an architected way of showing this condition. The SIGP SET ARCHITECTURE instruction is simply rejected. Linux as guest seems to not care about the return value, which is a good thing The new handling is just like already being in z/Architecture mode. We'll not try to fake absence of this facility, but still not indicate the facility in case some strange CPU model turned z/Architecture off completely (which doesn't work either way but let's us see how a guest would react on a lack of this facility). Signed-off-by: Jason J. Herne <jjherne@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-14s390x/cpumodel: wire up new hardware featuresJason J. Herne
Some new guest features have been introduced recently. Let's wire them up in the CPU model. Signed-off-by: Jason J. Herne <jjherne@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> [split patch]
2017-07-14s390x/cpumodel: add zpci, aen and ais facilitiesYi Min Zhao
zPCI instructions and facilities are available since IBM zEnterprise EC12. To support z/PCI in QEMU we enable zpci, aen and ais facilities starting with zEC12 GA1. And we always set zpci and aen bits in max cpu model. Later they might be switched off due to applied real cpu model. For ais bit, we only provide it in the full cpu model beginning with zEC12 and defer its enablement in the default cpu model to a later point in time. At the same time, disable them for 2.9 and older machines. Because of introducing AIS facility, we could check if it's enabled to initialize flic->ais_supported with the real value. Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com>
2017-07-14s390x/sic: realize SIC handlingFei Li
Currently, we do nothing for the SIC instruction, but we need to implement it properly. Let's add proper handling in the backend code. Co-authored-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Signed-off-by: Fei Li <sherrylf@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-14s390x/cpumodel: provide compat handling for new cpu featuresJason J. Herne
Provide a mechanism to disable features in compatibility machines. Signed-off-by: Jason J. Herne <jjherne@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-14s390x/cpumodel: clean up spacing and commentsJason J. Herne
Clean up spacing and add comments to clarify difference between base, full and default models. Not having spacing around the model definitions in gen-features.c is particularly frustrating as the reader tends to misinterpret which model they are looking at or editing. Signed-off-by: Jason J. Herne <jjherne@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-14qdev: Add const qualifier to PropertyInfo definitionsFam Zheng
The remaining non-const ones are in e1000e which modifies description at runtime. They can be addressed separatedly. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20170714021509.23681-6-famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-14char: add backend hotswap handlerAnton Nefedov
Frontends should have an interface to setup the handler of a backend change. The interface will be used in the next commits Signed-off-by: Anton Nefedov <anton.nefedov@virtuozzo.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <1499342940-56739-3-git-send-email-anton.nefedov@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-14Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2017-07-13' ↵Peter Maydell
into staging Error reporting patches for 2017-07-13 # gpg: Signature made Thu 13 Jul 2017 12:55:45 BST # gpg: using RSA key 0x3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2017-07-13: Convert error_report*_err() to warn_report*_err() error: Implement the warn and free Error functions char-socket: Report TCP socket waiting as information Convert error_report() to warn_report() error: Functions to report warnings and informational messages util/qemu-error: Rename error_print_loc() to be more generic websock: Don't try to set *errp directly block: Don't try to set *errp directly xilinx: Fix latent error handling bug Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-14s390x/kvm: Rework cmma managementJanosch Frank
Let's keep track of cmma enablement and move the mem_path check into the actual enablement. This now also warns users that do not use cpu-models about disabled cmma when using huge pages. Signed-off-by: Janosch Frank <frankja@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-13Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into ↵Peter Maydell
staging trivial patches for 2017-07-12 # gpg: Signature made Wed 12 Jul 2017 14:58:43 BST # gpg: using RSA key 0x701B4F6B1A693E59 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * remotes/mjt/tags/trivial-patches-fetch: include/hw/ptimer.h: Add documentation comments hxtool: remove dead -q option qga-win32: Fix memory leak of device information set hw/core: fix missing return value in load_image_targphys_as() elf-loader: warn about invalid endianness configure: Handle having no c++ compiler in FORTIFY_SOURCE check hw/pci: define msi_nonbroken in pci-stub hw/misc: add missing includes configure: Fix build with pkg-config and --static --enable-sdl util/qemu-sockets: Drop unused helper socket_address_to_string() target/xtensa: gdbstub: drop dead return statement Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-13Convert error_report() to warn_report()Alistair Francis
Convert all uses of error_report("warning:"... to use warn_report() instead. This helps standardise on a single method of printing warnings to the user. All of the warnings were changed using these two commands: find ./* -type f -exec sed -i \ 's|error_report(".*warning[,:] |warn_report("|Ig' {} + Indentation fixed up manually afterwards. The test-qdev-global-props test case was manually updated to ensure that this patch passes make check (as the test cases are case sensitive). Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Suggested-by: Thomas Huth <thuth@redhat.com> Cc: Jeff Cody <jcody@redhat.com> Cc: Kevin Wolf <kwolf@redhat.com> Cc: Max Reitz <mreitz@redhat.com> Cc: Ronnie Sahlberg <ronniesahlberg@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Lieven <pl@kamp.de> Cc: Josh Durgin <jdurgin@redhat.com> Cc: "Richard W.M. Jones" <rjones@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: Peter Crosthwaite <crosthwaite.peter@gmail.com> Cc: Richard Henderson <rth@twiddle.net> Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> Cc: Greg Kurz <groug@kaod.org> Cc: Rob Herring <robh@kernel.org> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Peter Chubb <peter.chubb@nicta.com.au> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alexander Graf <agraf@suse.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jason Wang <jasowang@redhat.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Cc: Cornelia Huck <cohuck@redhat.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Greg Kurz <groug@kaod.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Max Reitz <mreitz@redhat.com> Acked-by: Marcel Apfelbaum <marcel@redhat.com> Message-Id: <e1cfa2cd47087c248dd24caca9c33d9af0c499b0.1499866456.git.alistair.francis@xilinx.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2017-07-13Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170711' into stagingPeter Maydell
MIPS patches 2017-07-11 Changes: * Fix MSA copy_[s|u]_df corner case of rd = 0 * Update malta to load the initrd at the end of the low memory # gpg: Signature made Tue 11 Jul 2017 15:42:20 BST # gpg: using RSA key 0x2238EB86D5F797C2 # gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2 * remotes/yongbok/tags/mips-20170711: mips/malta: load the initrd at the end of the low memory target/mips: fix msa copy_[s|u]_df rd = 0 corner case Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-13Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20170711' into staging target-arm queue: * v7M: ignore writes to CONTROL.SPSEL from Thread mode * KVM: Enable in-kernel timers with user space gic * aspeed: Register all watchdogs * hw/misc: Add Exynos4210 Pseudo Random Number Generator # gpg: Signature made Tue 11 Jul 2017 11:28:15 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170711: target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode ARM: KVM: Enable in-kernel timers with user space gic aspeed: Register all watchdogs hw/misc: Add Exynos4210 Pseudo Random Number Generator Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-11target/mips: fix msa copy_[s|u]_df rd = 0 corner caseMiodrag Dinic
This patch fixes the msa copy_[s|u]_df instruction emulation when the destination register rd is zero. Without this patch the zero register would get clobbered, which should never happen because it is supposed to be hardwired to 0. Fix this corner case by explicitly checking rd = 0 and effectively making these instructions emulation no-op in that case. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-11target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread modePeter Maydell
For v7M, writes to the CONTROL register are only permitted for privileged code. However even if the code is privileged, the write must not affect the SPSEL bit in the CONTROL register if the CPU is in Thread mode (as documented in the pseudocode for the MSR instruction). Implement this, instead of permitting SPSEL to be written in all cases. This was causing mbed applications not to run, because the RTX RTOS they use relies on this behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1498820791-8130-1-git-send-email-peter.maydell@linaro.org
2017-07-11ARM: KVM: Enable in-kernel timers with user space gicAlexander Graf
When running with KVM enabled, you can choose between emulating the gic in kernel or user space. If the kernel supports in-kernel virtualization of the interrupt controller, it will default to that. If not, if will default to user space emulation. Unfortunately when running in user mode gic emulation, we miss out on interrupt events which are only available from kernel space, such as the timer. This patch leverages the new kernel/user space pending line synchronization for timer events. It does not handle PMU events yet. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1498577737-130264-1-git-send-email-agraf@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-11target/xtensa: gdbstub: drop dead return statementMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-07-11ppc/kvm: have the "family" CPU alias to point to TYPE_HOST_POWERPC_CPUGreg Kurz
When running KVM on POWER, we allow the user to pass "-cpu POWERx" instead of "-cpu host". This is achieved by patching the ppc_cpu_aliases[] array so that "POWERx" points to the CPU class with the same PVR as the host CPU. This causes CPUs to be instantiated from this CPU class instead of the TYPE_HOST_POWERPC_CPU class which is used with "-cpu host". These CPUs thus miss all the KVM specific tuning from kvmppc_host_cpu_class_init(). This currently causes QEMU with "-cpu POWER9" to fail when running KVM on a POWER9 DD1 host: qemu-system-ppc64: Register sync failed... If you're using kvm-hv.ko, only "-cpu host" is possible kvm_init_vcpu failed: Invalid argument Let's have the "POWERx" alias to point to TYPE_HOST_POWERPC_CPU directly, so that "-cpu POWERx" instantiates CPUs from the same class as "-cpu host". Signed-off-by: Greg Kurz <groug@kaod.org> Tested-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-07-11target/ppc: Add debug function for radix mmu translationSuraj Jitindar Singh
In target/ppc/mmu-hash64.c there already exists the function ppc_hash64_get_phys_page_debug() to get the physical (real) address for a given effective address in hash mode. Implement the function ppc_radix64_get_phys_page_debug() to allow a real address to be obtained for a given effective address in radix mode. This is used when a debugger is attached to qemu. Previously we just had a comment saying this is unimplemented which then fell through to the default case and caused an abort due to unrecognised mmu model as the default had no case for the V3 mmu, which was misleading at best. We reuse ppc_radix64_walk_tree() which is used by the radix fault handler since the process of walking the radix tree is identical. Reported-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-07-11target/ppc: Refactor tcg radix mmu codeSuraj Jitindar Singh
The mmu-radix64.c file implements functions to enable the radix mmu emulation in tcg mode. There is a function ppc_radix64_walk_tree() which performs the radix tree walk and also implicitly checks the pte protection. Move the protection checking of the pte from the ppc_radix64_walk_tree() function into the caller. This means the ppc_radix64_walk_tree() function can be used without protection checking which is useful for debugging. ppc_radix64_walk_tree() no longer needs to take the rwx and prot variables. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-07-11target-ppc: SPR_BOOKE_ESR not set on FP exceptionsAaron Larson
Properly set the book E exception syndrome register when a floating point exception occurs. Currently on a book E processor, the POWERPC_EXCP_FP exception handler fails to set "env->spr[SPR_BOOKE_ESR] = ESR_FP;" as required by the book E specification. Signed-off-by: Aaron Larson <alarson@ddci.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-07-06Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20170706' into ↵Peter Maydell
staging s390x/kvm/migration: fixes, enhancements and cleanups - new email address for Cornelia - Fixes: 3270, flic, virtio-scsi-ccw, ipl - Enhancements, cpumodel, migration # gpg: Signature made Thu 06 Jul 2017 08:18:19 BST # gpg: using RSA key 0x117BBC80B5A61C7C # gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>" # Primary key fingerprint: F922 9381 A334 08F9 DBAB FBCA 117B BC80 B5A6 1C7C * remotes/borntraeger/tags/s390x-20170706: hw/s390x/ipl: Fix endianness problem with netboot_start_addr virtio-scsi-ccw: use ioeventfd even when KVM is disabled s390x: return unavailable features via query-cpu-definitions s390x/MAINTAINERS: Update my email address s390x: fix realize inheritance for kvm-flic s390x: fix error propagation in kvm-flic's realize s390x/3270: fix instruction interception handler s390x: vmstatify config migration for virtio-ccw Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-06Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* qemu-thread portability improvement (Fam) * virtio-scsi IOMMU fix (Jason) * poisoning and common-obj-y cleanups (Thomas) * initial Hypervisor.framework refactoring (Sergio) * x86 TCG interrupt injection fixes (Wu Xiang, me) * --disable-tcg support for x86 (Yang Zhong, me) * various other bugfixes and cleanups (Daniel, Peter, Thomas) # gpg: Signature made Wed 05 Jul 2017 08:12:56 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (42 commits) target/i386: add the CONFIG_TCG into Makefiles target/i386: add the tcg_enabled() in target/i386/ target/i386: move TLB refill function out of helper.c target/i386: split cpu_set_mxcsr() and make cpu_set_fpuc() inline target/i386: make cpu_get_fp80()/cpu_set_fp80() static target/i386: move cpu_sync_bndcs_hflags() function tcg: add the CONFIG_TCG into Makefiles tcg: add CONFIG_TCG guards in headers exec: elide calls to tb_lock and tb_unlock tcg: move tb_lock out of translate-all.h tcg: add the tcg-stub.c file into accel/stubs/ vapic: use tcg_enabled monitor: disable "info jit" and "info opcount" if !TCG tcg: make tcg_allowed global cpu: move interrupt handling out of translate-common.c tcg: move page_size_init() function vl: add tcg_enabled() for tcg related code vl: convert -tb-size to qemu_strtoul configure: add --disable-tcg configure option configure: early test for supported targets ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-05virtio-scsi-ccw: use ioeventfd even when KVM is disabledQingFeng Hao
This patch is based on a similar patch from Stefan Hajnoczi - commit c324fd0a39c ("virtio-pci: use ioeventfd even when KVM is disabled") Do not check kvm_eventfds_enabled() when KVM is disabled since it always returns 0. Since commit 8c56c1a592b5092d91da8d8943c17777d6462a6f ("memory: emulate ioeventfd") it has been possible to use ioeventfds in qtest or TCG mode. This patch makes -device virtio-scsi-ccw,iothread=iothread0 work even when KVM is disabled. Currently we don't have an equivalent to "memory: emulate ioeventfd" for ccw yet, but that this doesn't hurt and qemu-iotests 068 can pass with skipping iothread arguments. I have tested that virtio-scsi-ccw works under tcg both with and without iothread. This patch fixes qemu-iotests 068, which was accidentally merged early despite the dependency on ioeventfd. Signed-off-by: QingFeng Hao <haoqf@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20170704132350.11874-2-haoqf@linux.vnet.ibm.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-05s390x: return unavailable features via query-cpu-definitionsViktor Mihajlovski
The response for query-cpu-definitions didn't include the unavailable-features field, which is used by libvirt to figure out whether a certain cpu model is usable on the host. The unavailable features are now computed by obtaining the host CPU model and comparing it against the known CPU models. The comparison takes into account the generation, the GA level and the feature bitmaps. In the case of a CPU generation/GA level mismatch a feature called "type" is reported to be missing. As a result, the output of virsh domcapabilities would change from something like ... <mode name='custom' supported='yes'> <model usable='unknown'>z10EC-base</model> <model usable='unknown'>z9EC-base</model> <model usable='unknown'>z196.2-base</model> <model usable='unknown'>z900-base</model> <model usable='unknown'>z990</model> ... to ... <mode name='custom' supported='yes'> <model usable='yes'>z10EC-base</model> <model usable='yes'>z9EC-base</model> <model usable='no'>z196.2-base</model> <model usable='yes'>z900-base</model> <model usable='yes'>z990</model> ... Signed-off-by: Viktor Mihajlovski <mihajlov@linux.vnet.ibm.com> Message-Id: <1499082529-16970-1-git-send-email-mihajlov@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-07-05target/i386: add the CONFIG_TCG into MakefilesYang Zhong
Add the CONFIG_TCG for frontend and backend's files in the related Makefiles. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-05target/i386: add the tcg_enabled() in target/i386/Yang Zhong
Add the tcg_enabled() where the x86 target needs to disable TCG-specific code. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-05target/i386: move TLB refill function out of helper.cPaolo Bonzini
This function calls tlb_set_page_with_attrs, which is not available when TCG is disabled. Move it to excp_helper.c. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-05target/i386: split cpu_set_mxcsr() and make cpu_set_fpuc() inlineYang Zhong
Split the cpu_set_mxcsr() and make cpu_set_fpuc() inline with specific tcg code. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-05target/i386: make cpu_get_fp80()/cpu_set_fp80() staticYang Zhong
Move cpu_get_fp80()/cpu_set_fp80() from fpu_helper.c to machine.c because fpu_helper.c will be disabled if tcg is disabled in the build. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-05target/i386: move cpu_sync_bndcs_hflags() functionYang Zhong
Move cpu_sync_bndcs_hflags() function from mpx_helper.c to helper.c because mpx_helper.c need be disabled when tcg is disabled. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-04xsave_helper: pull xsave and xrstor out of kvm.c into helper functionSergio Andres Gomez Del Real
This patch pulls out of kvm.c and into the new files the implementation for the xsave and xrstor instructions. This so they can be shared by kvm and hvf. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170626200832.11058-1-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Sergio Andres Gomez Del Real <sergio.g.delreal@gmail.com>
2017-07-04Move CONFIG_KVM related definitions to kvm_i386.hThomas Huth
pc.h and sysemu/kvm.h are also included from common code (where CONFIG_KVM is not available), so the #defines that depend on CONFIG_KVM should not be declared here to avoid that anybody is using them in a wrong way. Since we're also going to poison CONFIG_KVM for common code, let's move them to kvm_i386.h instead. Most of the dummy definitions from sysemu/kvm.h are also unused since the code that uses them is only compiled for CONFIG_KVM (e.g. target/i386/kvm.c), so the unused defines are also simply dropped here instead of being moved. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1498454578-18709-3-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-04target/i386: simplify handling of conforming code segments on interruptPaolo Bonzini
Move the handling of conforming code segments before the handling of stack switch. Because dpl == cpl after the new "if", it's now unnecessary to check the C bit when testing dpl < cpl. Furthermore, dpl > cpl is checked slightly above the modified code, so the final "else" is unreachable and we can remove it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-04target/i386: fix interrupt CPL error when using ist in x86-64Wu Xiang
In do_interrupt64(), when interrupt stack table(ist) is enabled and the the target code segment is conforming(e2 & DESC_C_MASK), the old implementation always set new CPL to 0, and SS.RPL to 0. This is incorrect for when CPL3 code access a CPL0 conforming code segment, the CPL should remain unchanged. Otherwise higher privileged code can be compromised. The patch fix this for always set dpl = cpl when the target code segment is conforming, and modify the last parameter `flags`, which contains correct new CPL, in cpu_x86_load_seg_cache(). Signed-off-by: Wu Xiang <willx8@gmail.com> Message-Id: <20170621142152.GA18094@wxdeubuntu.ipads-lab.se.sjtu.edu.cn> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-04vcpu_dirty: share the same field in CPUState for all acceleratorsSergio Andres Gomez Del Real
This patch simply replaces the separate boolean field in CPUState that kvm, hax (and upcoming hvf) have for keeping track of vcpu dirtiness with a single shared field. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170618191101.3457-1-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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