qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2021-06-16	bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations	Peter Maydell
2021-06-16	target/arm: Move expand_pred_b() data to vec_helper.c	Peter Maydell
2021-06-16	target/arm: Add framework for MVE decode	Peter Maydell
2021-06-16	target/arm: Implement MVE LETP insn	Peter Maydell
2021-06-16	target/arm: Implement MVE DLSTP	Peter Maydell
2021-06-16	target/arm: Implement MVE WLSTP insn	Peter Maydell
2021-06-16	target/arm: Implement MVE LCTP	Peter Maydell
2021-06-16	target/arm: Let vfp_access_check() handle late NOCP checks	Peter Maydell
2021-06-16	target/arm: Add handling for PSR.ECI/ICI	Peter Maydell
2021-06-16	target/arm: Handle VPR semantics in existing code	Peter Maydell
2021-06-16	target/arm: Enable FPSCR.QC bit for MVE	Peter Maydell
2021-06-16	target/arm: Provide and use H8 and H1_8 macros	Peter Maydell
2021-06-16	target/arm: Fix mte page crossing test	Richard Henderson
2021-06-15	target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16	Richard Henderson
2021-06-15	target/arm: Remove fprintf from disas_simd_mod_imm	Richard Henderson
2021-06-15	target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16	Richard Henderson
2021-06-08	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...	Peter Maydell
2021-06-08	target/riscv: rvb: add b-ext version cpu option	Frank Chang
2021-06-08	target/riscv: rvb: support and turn on B-extension from command line	Kito Cheng
2021-06-08	target/riscv: rvb: add/shift with prefix zero-extend	Kito Cheng
2021-06-08	target/riscv: rvb: address calculation	Kito Cheng
2021-06-08	target/riscv: rvb: generalized or-combine	Frank Chang
2021-06-08	target/riscv: rvb: generalized reverse	Frank Chang
2021-06-08	target/riscv: rvb: rotate (left/right)	Kito Cheng
2021-06-08	target/riscv: rvb: shift ones	Kito Cheng
2021-06-08	target/riscv: rvb: single-bit instructions	Frank Chang
2021-06-08	target/riscv: add gen_shifti() and gen_shiftiw() helper functions	Frank Chang
2021-06-08	target/riscv: rvb: sign-extend instructions	Kito Cheng
2021-06-08	target/riscv: rvb: min/max instructions	Kito Cheng
2021-06-08	target/riscv: rvb: pack two words into one register	Kito Cheng
2021-06-08	target/riscv: rvb: logic-with-negate	Kito Cheng
2021-06-08	target/riscv: rvb: count bits set	Frank Chang
2021-06-08	target/riscv: rvb: count leading/trailing zeros	Kito Cheng
2021-06-08	target/riscv: reformat @sh format encoding for B-extension	Kito Cheng
2021-06-08	target/riscv: Pass the same value to oprsz and maxsz.	LIU Zhiwei
2021-06-08	target/riscv/pmp: Add assert for ePMP operations	Alistair Francis
2021-06-08	target/riscv: Dump CSR mscratch/sscratch/satp	Changbin Du
2021-06-08	target/riscv: Remove unnecessary riscv_*_names[] declaration	Bin Meng
2021-06-08	target/riscv: Do not include 'pmp.h' in user emulation	Philippe Mathieu-Daudé
2021-06-08	target/riscv: fix wfi exception behavior	Jose Martins
2021-06-05	target/mips: Fix 'Uncoditional' typo	Philippe Mathieu-Daudé
2021-06-05	target/hppa: Remove unused 'memory.h' header	Philippe Mathieu-Daudé
2021-06-05	target/nios2: fix page-fit instruction count	Pavel Dovgalyuk
2021-06-05	target/riscv: Do not include 'pmp.h' in user emulation	Philippe Mathieu-Daudé
2021-06-04	i386: run accel_cpu_instance_init as post_init	Claudio Fontana
2021-06-04	i386: reorder call to cpu_exec_realizefn	Claudio Fontana
2021-06-04	target/i386: Fix decode of cr8	Richard Henderson
2021-06-04	target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa	Paolo Bonzini
2021-06-04	target/i386: tcg: fix loading of registers from 16-bit TSS	Paolo Bonzini
2021-06-04	target/i386: tcg: fix segment register offsets for 16-bit TSS	Paolo Bonzini