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AgeCommit message (Expand)Author
2019-03-29target/ppc: Fix QEMU crash with stxsdxGreg Kurz
2019-03-29target/ppc: Improve comment of bcctr used for spectre v2 mitigationGreg Kurz
2019-03-29target/ppc: Consolidate 64-bit server processor detection in a helperGreg Kurz
2019-03-29target/ppc: Enable "decrement and test CTR" version of bcctrGreg Kurz
2019-03-29target/ppc: Fix TCG temporary leaks in gen_bcond()Greg Kurz
2019-03-28Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2019-03-28Merge remote-tracking branch 'remotes/xtensa/tags/20190326-xtensa' into stagingPeter Maydell
2019-03-26target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu maxRichard Henderson
2019-03-26target/riscv: Fix wrong expanding for c.fswspKito Cheng
2019-03-26Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc1' i...Peter Maydell
2019-03-25Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int...Peter Maydell
2019-03-25target/arm: make pmccntr_op_start/finish staticAndrew Jones
2019-03-25target/arm: cortex-a7 and cortex-a15 have pmusAndrew Jones
2019-03-25target/arm: fix crash on pmu register accessAndrew Jones
2019-03-25target/arm: Fix non-parallel expansion of CASPRichard Henderson
2019-03-23target/xtensa: don't announce exit simcallMax Filippov
2019-03-22trace-events: Shorten file names in commentsMarkus Armbruster
2019-03-22target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt
2019-03-21target/xtensa: fix break_dependency for repeated resourcesMax Filippov
2019-03-20i386: Disable OSPKE on CPU model definitionsEduardo Habkost
2019-03-20i386: Make arch_capabilities migratableEduardo Habkost
2019-03-20i386: kvm: Disable arch_capabilities if MSR can't be setEduardo Habkost
2019-03-19target/riscv: Remove unused structAlistair Francis
2019-03-19RISC-V: Update load reservation comment in do_interruptMichael Clark
2019-03-19RISC-V: Convert trap debugging to trace eventsMichael Clark
2019-03-19RISC-V: Add support for vectored interruptsMichael Clark
2019-03-19RISC-V: Change local interrupts from edge to levelMichael Clark
2019-03-19RISC-V: linux-user support for RVE ABIKito Cheng
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark
2019-03-19riscv: pmp: Log pmp access errors as guest errorsAlistair Francis
2019-03-19RISC-V: Add hooks to use the gdb xml files.Jim Wilson
2019-03-19RISC-V: Add debug support for accessing CSRs.Jim Wilson
2019-03-19RISC-V: Fixes to CSR_* register macros.Jim Wilson
2019-03-18target/i386: sev: Do not pin the ram device memory regionSingh, Brijesh
2019-03-17target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann
2019-03-15target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXITRichard Henderson
2019-03-15target/arm: Check access permission to ADDVL/ADDPL/RDVLAmir Charif
2019-03-15target/arm: change arch timer registers access permissionDongjiu Geng
2019-03-13Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' i...Peter Maydell
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann
2019-03-13target/riscv: Remove gen_system()Bastian Koppelmann
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann