qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2021-05-12	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...	Peter Maydell
2021-05-12	Drop the deprecated unicore32 target	Markus Armbruster
2021-05-12	Drop the deprecated lm32 target	Markus Armbruster
2021-05-12	Remove the deprecated moxie target	Thomas Huth
2021-05-11	target/riscv: Fix the RV64H decode comment	Alistair Francis
2021-05-11	target/riscv: Consolidate RV32/64 16-bit instructions	Alistair Francis
2021-05-11	target/riscv: Consolidate RV32/64 32-bit instructions	Alistair Francis
2021-05-11	target/riscv: Remove an unused CASE_OP_32_64 macro	Alistair Francis
2021-05-11	target/riscv: Remove the unused HSTATUS_WPRI macro	Alistair Francis
2021-05-11	target/riscv: Remove the hardcoded SATP_MODE macro	Alistair Francis
2021-05-11	target/riscv: Remove the hardcoded MSTATUS_SD macro	Alistair Francis
2021-05-11	target/riscv: Remove the hardcoded HGATP_MODE macro	Alistair Francis
2021-05-11	target/riscv: Remove the hardcoded SSTATUS_SD macro	Alistair Francis
2021-05-11	target/riscv: Remove the hardcoded RVXLEN macro	Alistair Francis
2021-05-11	target/riscv: fix a typo with interrupt names	Emmanuel Blot
2021-05-11	target/riscv: fix exception index on instruction access fault	Emmanuel Blot
2021-05-11	target/riscv: fix vrgather macro index variable type bug	Frank Chang
2021-05-11	target/riscv: Add ePMP support for the Ibex CPU	Alistair Francis
2021-05-11	target/riscv/pmp: Remove outdated comment	Alistair Francis
2021-05-11	target/riscv: Add a config option for ePMP	Hou Weiying
2021-05-11	target/riscv: Implementation of enhanced PMP (ePMP)	Hou Weiying
2021-05-11	target/riscv: Add ePMP CSR access functions	Hou Weiying
2021-05-11	target/riscv: Add the ePMP feature	Alistair Francis
2021-05-11	target/riscv: Define ePMP mseccfg	Hou Weiying
2021-05-11	target/riscv: Fix the PMP is locked check when using TOR	Alistair Francis
2021-05-11	target/riscv: Fixup saturate subtract function	LIU Zhiwei
2021-05-11	riscv: don't look at SUM when accessing memory from a debugger context	Jade Fink
2021-05-11	target/riscv: Use RISCVException enum for CSR access	Alistair Francis
2021-05-11	target/riscv: Use the RISCVException enum for CSR operations	Alistair Francis
2021-05-11	target/riscv: Fix 32-bit HS mode access permissions	Alistair Francis
2021-05-11	target/riscv: Use the RISCVException enum for CSR predicates	Alistair Francis
2021-05-11	target/riscv: Convert the RISC-V exceptions to an enum	Alistair Francis
2021-05-11	target/riscv: Add Shakti C class CPU	Vijai Kumar K
2021-05-11	target/riscv: Align the data type of reset vector address	Dylan Jhong
2021-05-11	target/riscv: Remove privilege v1.9 specific CSR related code	Atish Patra
2021-05-11	target/i386: use mmu_translate for NPT walk	Paolo Bonzini
2021-05-11	target/i386: allow customizing the next phase of the translation	Paolo Bonzini
2021-05-11	target/i386: extend pg_mode to more CR0 and CR4 bits	Paolo Bonzini
2021-05-11	target/i386: pass cr3 to mmu_translate	Paolo Bonzini
2021-05-11	target/i386: extract mmu_translate	Paolo Bonzini
2021-05-11	target/i386: move paging mode constants from SVM to cpu.h	Paolo Bonzini
2021-05-11	target/i386: merge SVM_NPTEXIT_* with PF_ERROR_* constants	Paolo Bonzini
2021-05-10	accel: add init_accel_cpu for adapting accel behavior to CPU type	Claudio Fontana
2021-05-10	i386: make cpu_load_efer sysemu-only	Claudio Fontana
2021-05-10	target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemu	Claudio Fontana
2021-05-10	target/i386: gdbstub: introduce aux functions to read/write CS64 regs	Claudio Fontana
2021-05-10	i386: split off sysemu part of cpu.c	Claudio Fontana
2021-05-10	i386: split seg_helper into user-only and sysemu parts	Claudio Fontana
2021-05-10	i386: split svm_helper into sysemu and stub-only user	Claudio Fontana
2021-05-10	i386: separate fpu_helper sysemu-only parts	Claudio Fontana