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AgeCommit message (Expand)Author
2021-05-01Hexagon (target/hexagon) add A6_vminub_RdPTaylor Simpson
2021-05-01Hexagon (target/hexagon) add A5_ACS (vacsh)Taylor Simpson
2021-05-01Hexagon (target/hexagon) add F2_sfinvsqrtaTaylor Simpson
2021-05-01Hexagon (target/hexagon) add F2_sfrecipa instructionTaylor Simpson
2021-05-01Hexagon (target/hexagon) compile all debug codeTaylor Simpson
2021-05-01Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.hTaylor Simpson
2021-05-01Hexagon (target/hexagon) cleanup reg_field_info definitionTaylor Simpson
2021-05-01Hexagon (target/hexagon) cleanup ternary operators in semanticsTaylor Simpson
2021-05-01Hexagon (target/hexagon) use softfloat for float-to-int conversionsTaylor Simpson
2021-05-01Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbnTaylor Simpson
2021-05-01Hexagon (target/hexagon) use softfloat default NaN and tininessTaylor Simpson
2021-05-01Hexagon (target/hexagon) change type of softfloat_roundingmodesTaylor Simpson
2021-05-01Hexagon (target/hexagon) remove unused carry_from_add64 functionTaylor Simpson
2021-05-01Hexagon (target/hexagon) change variables from int to bool when appropriateTaylor Simpson
2021-05-01Hexagon (target/hexagon) decide if pred has been written at TCG gen timeTaylor Simpson
2021-05-01Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURNTaylor Simpson
2021-05-01Hexagon (target/hexagon) use env_archcpu and env_cpuTaylor Simpson
2021-05-01Hexagon (target/hexagon) remove unnecessary inline directivesTaylor Simpson
2021-05-01Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pairTaylor Simpson
2021-05-01Hexagon (target/hexagon) TCG generation cleanupTaylor Simpson
2021-05-01target/hexagon: remove unnecessary semicolonsTaylor Simpson
2021-05-01target/hexagon: fix typo in commentTaylor Simpson
2021-05-01target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUMTaylor Simpson
2021-05-01target/hexagon: remove unnecessary checks in find_iclass_slotsTaylor Simpson
2021-05-01target/hexagon: translation changesTaylor Simpson
2021-04-30target/arm: Enforce alignment for sve LD1RRichard Henderson
2021-04-30target/arm: Enforce alignment for aa64 vector LDn/STn (single)Richard Henderson
2021-04-30target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)Richard Henderson
2021-04-30target/arm: Use MemOp for size + endian in aa64 vector ld/stRichard Henderson
2021-04-30target/arm: Enforce alignment for aa64 load-acq/store-relRichard Henderson
2021-04-30target/arm: Use finalize_memop for aa64 fpr load/storeRichard Henderson
2021-04-30target/arm: Use finalize_memop for aa64 gpr load/storeRichard Henderson
2021-04-30target/arm: Enforce alignment for VLDn/VSTn (single)Richard Henderson
2021-04-30target/arm: Enforce alignment for VLDn/VSTn (multiple)Richard Henderson
2021-04-30target/arm: Enforce alignment for VLDn (all lanes)Richard Henderson
2021-04-30target/arm: Enforce alignment for VLDR/VSTRRichard Henderson
2021-04-30target/arm: Enforce alignment for VLDM/VSTMRichard Henderson
2021-04-30target/arm: Enforce alignment for SRSRichard Henderson
2021-04-30target/arm: Enforce alignment for RFERichard Henderson
2021-04-30target/arm: Enforce alignment for LDM/STMRichard Henderson
2021-04-30target/arm: Enforce alignment for LDA/LDAH/STL/STLHRichard Henderson
2021-04-30target/arm: Enforce word alignment for LDRD/STRDRichard Henderson
2021-04-30target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endiannessRichard Henderson
2021-04-30target/arm: Fix SCTLR_B test for TCGv_i64 load/storeRichard Henderson
2021-04-30target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64Richard Henderson
2021-04-30target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endiannessRichard Henderson
2021-04-30target/arm: Add ALIGN_MEM to TBFLAG_ANYRichard Henderson
2021-04-30target/arm: Move TBFLAG_ANY bits to the bottomRichard Henderson
2021-04-30target/arm: Move TBFLAG_AM32 bits to the topRichard Henderson
2021-04-30target/arm: Move mode specific TB flags to tb->cs_baseRichard Henderson