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path: root/target/xtensa/translate.c
AgeCommit message (Expand)Author
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé
2020-01-06target/xtensa: fix ps.ring use in MPU configsMax Filippov
2019-10-28target/xtensa: fetch code with translator_ldEmilio G. Cota
2019-08-20icount: remove unnecessary gen_io_end callsPavel Dovgalyuk
2019-08-16Clean up inclusion of sysemu/sysemu.hMarkus Armbruster
2019-05-28semihosting: move semihosting configuration into its own directoryAlex Bennée
2019-05-21Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into stagingPeter Maydell
2019-05-15target/xtensa: implement exclusive access optionMax Filippov
2019-05-15target/xtensa: implement block prefetch option opcodesMax Filippov
2019-05-14target/xtensa: implement DIWBUI.P opcodeMax Filippov
2019-05-13target/xtensa: Use tcg_gen_abs_i32Richard Henderson
2019-05-10target/xtensa: implement MPU optionMax Filippov
2019-05-10target/xtensa: add parity/ECC option SRsMax Filippov
2019-05-10target/xtensa: get rid of centralized SR propertiesMax Filippov
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster
2019-03-21target/xtensa: fix break_dependency for repeated resourcesMax Filippov
2019-02-28target/xtensa: implement PREFCTL SRMax Filippov
2019-02-28target/xtensa: prioritize load/store in FLIX bundlesMax Filippov
2019-02-28target/xtensa: break circular register dependenciesMax Filippov
2019-02-28target/xtensa: reorganize access to boolean registersMax Filippov
2019-02-28target/xtensa: reorganize access to MAC16 registersMax Filippov
2019-02-28target/xtensa: reorganize register handling in translatorsMax Filippov
2019-02-28target/xtensa: only rotate window in the retw helperMax Filippov
2019-02-28target/xtensa: move WINDOW_BASE SR update to postprocessingMax Filippov
2019-02-28target/xtensa: add generic instruction post-processingMax Filippov
2019-02-28target/xtensa: sort FLIX instruction opcodesMax Filippov
2019-02-18target/xtensa: implement wide branches and loopsMax Filippov
2019-02-18target/xtensa: allow multiple names for single opcodeMax Filippov
2019-02-18target/xtensa: don't require opcode table sortingMax Filippov
2019-02-11target/xtensa: get rid of gen_callw[i]Max Filippov
2019-02-10target/xtensa: don't specify windowed registers manuallyMax Filippov
2019-01-24target/xtensa: fix access to the INTERRUPT SRMax Filippov
2019-01-11target/xtensa: rework zero overhead loops implementationMax Filippov
2018-10-01target/xtensa: extract gen_check_interrupts callMax Filippov
2018-10-01target/xtensa: make rsr/wsr helpers return voidMax Filippov
2018-10-01target/xtensa: extract unconditional TB termination via slot 0Max Filippov
2018-10-01target/xtensa: always end TB on CCOUNT access/CCOMPARE writeMax Filippov
2018-10-01target/xtensa: change SR number checks to assertionsMax Filippov
2018-10-01target/xtensa: extract unconditional TB terminationMax Filippov
2018-10-01target/xtensa: extract test for division by zeroMax Filippov
2018-10-01target/xtensa: extract test for cpdisabled exceptionMax Filippov
2018-10-01target/xtensa: extract test for alloca exceptionMax Filippov
2018-10-01target/xtensa: extract test for window underflow exceptionMax Filippov
2018-10-01target/xtensa: extract test for window overflow exceptionMax Filippov
2018-10-01target/xtensa: extract test for debug exceptionMax Filippov
2018-10-01target/xtensa: extract test for syscall instructionMax Filippov
2018-10-01target/xtensa: extract test for privileged instructionMax Filippov
2018-10-01target/xtensa: extract test for an illegal instructionMax Filippov
2018-09-17target/xtensa: fix s32c1i TCGMemOp flagsMax Filippov