summaryrefslogtreecommitdiff
path: root/target/sparc
AgeCommit message (Expand)Author
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota
2017-10-24target/sparc: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson
2017-10-24tcg: Remove GET_TCGV_* and MAKE_TCGV_*Richard Henderson
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé
2017-09-27migration: pre_save return intDr. David Alan Gilbert
2017-09-14sparc: Fix typedef clashDr. David Alan Gilbert
2017-09-01sparc: replace cpu_sparc_init() with cpu_generic_init()Igor Mammedov
2017-09-01sparc: make cpu feature parsing property basedIgor Mammedov
2017-09-01sparc: move adhoc CPUSPARCState initialization to realize timeIgor Mammedov
2017-09-01sparc: convert cpu features to qdev propertiesIgor Mammedov
2017-09-01sparc: embed sparc_def_t into CPUSPARCStateIgor Mammedov
2017-09-01sparc: convert cpu models to SPARC cpu subclassesIgor Mammedov
2017-08-01trace-events: fix code style: print 0x before hex numbersVladimir Sementsov-Ogievskiy
2017-07-31docs: fix broken paths to docs/devel/tracing.txtPhilippe Mathieu-Daudé
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
2017-07-19target/sparc: optimize gen_op_mulscc() using deposit opPhilippe Mathieu-Daudé
2017-07-19target/sparc: optimize various functions using extract opPhilippe Mathieu-Daudé
2017-05-23shutdown: Add source information to SHUTDOWN and RESETEric Blake
2017-03-09sparc/sparc64: grab BQL before calling cpu_check_irqsAlex Bennée
2017-03-02target/sparc: Restore ldstub of odd asisRichard Henderson
2017-02-24cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmapAlex Bennée
2017-02-21monitor: Fix crashes when using HMP commands without CPUThomas Huth
2017-01-24migration: extend VMStateInfoJianjun Duan
2017-01-18target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUsArtyom Tarasenko
2017-01-18target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko
2017-01-18target-sparc: add more registers to dump_mmuArtyom Tarasenko
2017-01-18target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko
2017-01-18target-sparc: allow 256M sized pagesArtyom Tarasenko
2017-01-18target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 TSB PointersArtyom Tarasenko
2017-01-18target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko
2017-01-18target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko
2017-01-18target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko
2017-01-18target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko
2017-01-18target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko
2017-01-18target-sparc: fix immediate UA2005 trapsArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 GL registerArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko
2017-01-18target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko
2017-01-18target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko
2017-01-18target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko
2017-01-18target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko
2017-01-18target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko
2017-01-18target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko
2017-01-18target-sparc: use explicit mmu register pointersArtyom Tarasenko
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 19:54:37 +0000