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AgeCommit message (Expand)Author
2017-01-18target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko
2017-01-18target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko
2017-01-18target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko
2017-01-18target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko
2017-01-18target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko
2017-01-18target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko
2017-01-18target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko
2017-01-18target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko
2017-01-18target-sparc: use explicit mmu register pointersArtyom Tarasenko
2017-01-18target-sparc: store cpu super- and hypervisor flags in TBArtyom Tarasenko
2017-01-18target-sparc: ignore MMU-faults if MMU is disabled in hypervisor modeArtyom Tarasenko
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée
2017-01-10target-sparc: Use ctpop helperRichard Henderson
2016-12-20Move target-* CPU file into a target/ folderThomas Huth