qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2020-01-24	qdev: set properties with device_class_set_props()	Marc-André Lureau
2020-01-24	cpu: Use cpu_class_set_parent_reset()	Greg Kurz
2020-01-24	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' i...	Peter Maydell
2020-01-16	target/riscv: update mstatus.SD when FS is set dirty	ShihPo Hung
2020-01-16	target/riscv: fsd/fsw doesn't dirty FP state	ShihPo Hung
2020-01-16	target/riscv: Fix tb->flags FS status	ShihPo Hung
2020-01-16	riscv: Set xPIE to 1 after xRET	Yiting Wang
2020-01-15	tcg: Search includes from the project root source directory	Philippe Mathieu-Daudé
2019-11-14	target/riscv: Remove atomic accesses to MIP CSR	Alistair Francis
2019-11-14	remove unnecessary ifdef TARGET_RISCV64	hiroyuki.obinata
2019-10-30	Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-plugins-281019-4'...	Peter Maydell
2019-10-28	target/riscv: PMP violation due to wrong size parameter	Dayeol Lee
2019-10-28	target/riscv: fetch code with translator_ld	Emilio G. Cota
2019-10-28	target/riscv: Make the priv register writable by GDB	Jonathan Behrens
2019-10-28	target/riscv: Expose "priv" register for GDB for reads	Jonathan Behrens
2019-10-28	target/riscv: Tell gdbstub the correct number of CSRs	Jonathan Behrens
2019-10-28	linux-user/riscv: Propagate fault address	Giuseppe Musacchio
2019-10-28	RISC-V: Implement cpu_do_transaction_failed	Palmer Dabbelt
2019-10-28	RISC-V: Handle bus errors in the page table walker	Palmer Dabbelt
2019-10-28	riscv: Skip checking CSR privilege level in debugger mode	Bin Meng
2019-09-17	gdbstub: riscv: fix the fflags registers	KONRAD Frederic
2019-09-17	target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point	Alistair Francis
2019-09-17	target/riscv: Fix mstatus dirty mask	Alistair Francis
2019-09-17	target/riscv: Use both register name and ABI name	Atish Patra
2019-09-17	riscv: hmp: Add a command to show virtual memory mappings	Bin Meng
2019-09-17	riscv: rv32: Root page table address can be larger than 32-bit	Bin Meng
2019-09-17	target/riscv: Update the Hypervisor CSRs to v0.4	Alistair Francis
2019-09-17	target/riscv: Create function to test if FP is enabled	Alistair Francis
2019-09-17	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events	Philippe Mathieu-Daudé
2019-09-17	target/riscv/pmp: Restrict priviledged PMP to system-mode emulation	Philippe Mathieu-Daudé
2019-09-03	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen
2019-08-22	Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in...	Peter Maydell
2019-08-21	hw/core: Move cpu.c, cpu.h from qom/ to hw/core/	Markus Armbruster
2019-08-20	icount: remove unnecessary gen_io_end calls	Pavel Dovgalyuk
2019-08-19	Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20190819' into staging	Peter Maydell
2019-08-19	target/riscv: Remove redundant declaration pragmas	Richard Henderson
2019-08-19	target/riscv: rationalise softfloat includes	Alex Bennée
2019-06-25	RISC-V: Clear load reservations on context switch and SC	Joel Sing
2019-06-25	RISC-V: Add support for the Zicsr extension	Palmer Dabbelt
2019-06-25	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt
2019-06-25	target/riscv: Add support for disabling/enabling Counters	Alistair Francis
2019-06-25	target/riscv: Remove user version information	Alistair Francis
2019-06-25	target/riscv: Require either I or E base extension	Alistair Francis
2019-06-25	target/riscv: Set privledge spec 1.11.0 as default	Alistair Francis
2019-06-25	target/riscv: Add the mcountinhibit CSR	Alistair Francis
2019-06-24	target/riscv: Add the privledge spec version 1.11.0	Alistair Francis
2019-06-24	target/riscv: Restructure deprecatd CPUs	Alistair Francis
2019-06-23	RISC-V: Fix a PMP check with the correct access size	Hesham Almatary
2019-06-23	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	Hesham Almatary
2019-06-23	RISC-V: Check PMP during Page Table Walks	Hesham Almatary