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AgeCommit message (Expand)Author
2020-06-05target/riscv/cpu: Restrict CPU migration to system-modePhilippe Mathieu-Daudé
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton
2020-04-29riscv: Fix Stage2 SV32 page table walkAnup Patel
2020-04-29riscv: AND stage-1 and stage-2 protection flagsAlistair Francis
2020-04-29riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée
2020-03-16target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal
2020-03-16target/riscv: Correctly implement TSR trapAlistair Francis
2020-03-05RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis
2020-02-27target/riscv: Implement second stage MMUAlistair Francis
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis
2020-02-27target/riscv: Remove the hret instructionAlistair Francis
2020-02-27target/riscv: Add hfence instructionsAlistair Francis
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis
2020-02-27target/riscv: Add the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis
2020-02-25target/riscv: progressively load the instruction during decodeAlex Bennée
2020-02-10riscv: Separate FPU register size from core register size in gdbstub [v2]Keith Packard
2020-01-27Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
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