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path: root/target/riscv/csr.c
AgeCommit message (Expand)Author
2020-07-02target/riscv: support vector extension csrLIU Zhiwei
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis
2020-01-16target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis
2019-10-28riscv: Skip checking CSR privilege level in debugger modeBin Meng
2019-09-17target/riscv: Fix mstatus dirty maskAlistair Francis
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis
2019-06-25target/riscv: Add the mcountinhibit CSRAlistair Francis
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson
2019-05-24target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens
2019-05-24target/riscv: More accurate handling of `sip` CSRJonathan Behrens
2019-05-24target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis
2019-05-24target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis
2019-03-19RISC-V: Add support for vectored interruptsMichael Clark
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark
2019-03-19RISC-V: Add debug support for accessing CSRs.Jim Wilson
2019-02-11target/riscv: fix counter-enable checks in ctr()Xi Wang
2019-02-11RISC-V: Add misa runtime write supportMichael Clark
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark
2019-02-11RISC-V: Mark mstatus.fs dirtyRichard Henderson
2019-01-09RISC-V: Implement existential predicates for CSRsMichael Clark
2019-01-09RISC-V: Implement atomic mip/sip CSR updatesMichael Clark
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark
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