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2018-06-04Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into ↵Peter Maydell
staging tcg-next queue # gpg: Signature made Sat 02 Jun 2018 00:12:42 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/tcg-next-pull-request: tcg: Pass tb and index to tcg_gen_exit_tb separately Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-01target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé
Code change produced with: $ git grep '#include "exec/exec-all.h"' | \ cut -d: -f-1 | \ xargs egrep -L "(cpu_address_space_init|cpu_loop_|tlb_|tb_|GETPC|singlestep|TranslationBlock)" | \ xargs sed -i.bak '/#include "exec\/exec-all.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-10-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-14target/openrisc: Merge disas_openrisc_insnRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_floatRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_compiRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_compRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_MRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_logicRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_macRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert dec_calcRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert remainder of dec_misc insnsRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert memory insnsRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Convert branch insnsRichard Henderson
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target/openrisc: Start conversion to decodetree.pyRichard Henderson
Begin with the 0x08 major opcode, the system instructions. Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-14target-openrisc: Write back result before FPE exceptionRichard Henderson
The architecture manual is unclear about this, but the or1ksim does writeback before the exception. This requires splitting the helpers in half, with the exception raised by the second. Acked-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2018-05-09target/openrisc: convert to TranslatorOpsEmilio G. Cota
Notes: - Changed the num_insns test in insn_start to check for dc->base.num_insns > 1, since when tb_start is first called in a TB, base.num_insns is already set to 1. - Removed DISAS_NEXT from the switch in tb_stop; use DISAS_TOO_MANY instead. - Added an assert_not_reached on tb_stop for DISAS_NEXT and the default case. - Merged the two separate log_target_disas calls into the disas_log op. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Stafford Horne <shorne@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-09target/openrisc: convert to DisasContextBaseEmilio G. Cota
While at it, set is_jmp to DISAS_NORETURN when generating an exception. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Stafford Horne <shorne@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-04-11icount: fix cpu_restore_state_from_tb for non-tb-exit casesPavel Dovgalyuk
In icount mode, instructions that access io memory spaces in the middle of the translation block invoke TB recompilation. After recompilation, such instructions become last in the TB and are allowed to access io memory spaces. When the code includes instruction like i386 'xchg eax, 0xffffd080' which accesses APIC, QEMU goes into an infinite loop of the recompilation. This instruction includes two memory accesses - one read and one write. After the first access, APIC calls cpu_report_tpr_access, which restores the CPU state to get the current eip. But cpu_restore_state_from_tb resets the cpu->can_do_io flag which makes the second memory access invalid. Therefore the second memory access causes a recompilation of the block. Then these operations repeat again and again. This patch moves resetting cpu->can_do_io flag from cpu_restore_state_from_tb to cpu_loop_exit* functions. It also adds a parameter for cpu_restore_state which controls restoring icount. There is no need to restore icount when we only query CPU state without breaking the TB. Restoring it in such cases leads to the incorrect flow of the virtual time. In most cases new parameter is true (icount should be recalculated). But there are two cases in i386 and openrisc when the CPU state is only queried without the need to break the TB. This patch fixes both of these cases. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Message-Id: <20180409091320.12504.35329.stgit@pasha-VirtualBox> [rth: Make can_do_io setting unconditional; move from cpu_exec; make cpu_loop_exit_{noexc,restore} call cpu_loop_exit.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov
cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so no users are left, remove it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1518000027-274608-6-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov
it will be used for providing to cpu name resolving class for parsing cpu model for system and user emulation code. Along with change add target to null-machine tests, so that when switch to CPU_RESOLVING_TYPE happens, it would ensure that null-machine usecase still works. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> (m68k) Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Message-Id: <1518000027-274608-4-git-send-email-imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Added macro to riscv too] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée
As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé
changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier
The MC68040 MMU provides the size of the access that triggers the page fault. This size is set in the Special Status Word which is written in the stack frame of the access fault exception. So we need the size in m68k_cpu_unassigned_access() and m68k_cpu_handle_mmu_fault(). To be able to do that, this patch modifies the prototype of handle_mmu_fault handler, tlb_fill() and probe_write(). do_unassigned_access() already includes a size parameter. This patch also updates handle_mmu_fault handlers and tlb_fill() of all targets (only parameter, no code change). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
2017-12-27target/*helper: don't check retaddr before calling cpu_restore_stateAlex Bennée
cpu_restore_state officially supports being passed an address it can't resolve the state for. As a result the checks in the helpers are superfluous and can be removed. This makes the code consistent with other users of cpu_restore_state. Of course this does nothing to address what to do if cpu_restore_state can't resolve the state but so far it seems this is handled elsewhere. The change was made with included coccinelle script. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [rth: Fixed up comment indentation. Added second hunk to script to combine cpu_restore_state and cpu_loop_exit.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-12-18misc: remove duplicated includesPhilippe Mathieu-Daudé
exec: housekeeping (funny since 02d0e095031) applied using ./scripts/clean-includes Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-10-30Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86/cpu/numa queue, 2017-10-27 # gpg: Signature made Fri 27 Oct 2017 15:17:12 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: (39 commits) x86: Skip check apic_id_limit for Xen numa: fixup parsed NumaNodeOptions earlier mips: r4k: replace cpu_model with cpu_type mips: mipssim: replace cpu_model with cpu_type mips: Magnum/Acer Pica 61: replace cpu_model with cpu_type mips: fulong2e: replace cpu_model with cpu_type mips: malta/boston: replace cpu_model with cpu_type mips: use object_new() instead of gnew()+object_initialize() sparc: leon3: use generic cpu_model parsing sparc: sparc: use generic cpu_model parsing sparc: sun4u/sun4v/niagara: use generic cpu_model parsing sparc: cleanup cpu type name composition tricore: use generic cpu_model parsing tricore: cleanup cpu type name composition unicore32: use generic cpu_model parsing unicore32: cleanup cpu type name composition xtensa: lx60/lx200/ml605/kc705: use generic cpu_model parsing xtensa: sim: use generic cpu_model parsing xtensa: cleanup cpu type name composition sh4: remove SuperHCPUClass::name field ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-27openrisc: cleanup cpu type name compositionIgor Mammedov
use new OPENRISC_CPU_TYPE_NAME to compose CPU type name and get rid of intermediate OpenRISCCPUInfo/openrisc_cpu_register_types() which is replaced by static TypeInfo array. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1507211474-188400-18-git-send-email-imammedo@redhat.com> Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell
Capstone disassembler # gpg: Signature made Thu 26 Oct 2017 10:57:27 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dis-20171026: disas: Add capstone as submodule disas: Remove monitor_disas_is_physical ppc: Support Capstone in disas_set_info arm: Support Capstone in disas_set_info i386: Support Capstone in disas_set_info disas: Support the Capstone disassembler library disas: Remove unused flags arguments target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLY target/arm: Move BE32 disassembler fixup target/ppc: Convert to disas_set_info hook target/i386: Convert to disas_set_info hook Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/i386/cpu.c # target/ppc/translate_init.c
2017-10-25disas: Remove unused flags argumentsRichard Henderson
Now that every target is using the disas_set_info hook, the flags argument is unused. Remove it. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson
This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created by targets. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota
Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota
Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \ accel/tcg/translator.c | cut -f1 -d':' | sort | uniq) perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson
Move target cpu tcg initialization to common code, called from cpu_exec_realizefn. Acked-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne
In order to support multicore system we move some of the previously static state variables into the state of each core. On the other hand in order to allow timers to be synced between each code the ttcr (tick timer count register) is moved out of the core. This is not as per real hardware spec which has a separate timer counter per core, but it seems the most simple way to keep each clock in sync. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-10-21target/openrisc: Make coreid and numcores variableStafford Horne
Previously coreid and numcores were hard coded as 0 and 1 respectively as OpenRISC QEMU did not have multicore support. Multicore support is now being added so these registers need to have configured values. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé
and clean every implementation. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170917232842.14544-1-f4bug@amsat.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova
Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-01openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov
it's just a wrapper, drop it and use cpu_generic_init() directly Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1503592308-93913-24-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-05-04target/openrisc: Support non-busy idle state using PMR SPRStafford Horne
The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting modes are: * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt * Suspend Model (SUME) - Stop cpu and all units - wake on reset The linux kernel will set DME when idle. This patch implements the PMR SPR and halts the qemu cpu when there is a change to DME or SME. This means that openrisc qemu in no longer peggs a host cpu at 100%. In order for this to work we need to kick the CPU when timers are expired. Update the cpu timer to kick the cpu upon each timer event. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-05-04target/openrisc: Remove duplicate features propertyStafford Horne
The features property has stored the exact same thing as the cpucfgr spr. Remove the feature enum and property as it is not needed. In order to preserve the behavior or keeping features accross reset this patch moves cpucfgr into the non reset region of the state struct. Since the cpucfgr is read only this means we only need to sset cpucfgr once during class init. Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-05-04target/openrisc: Implement full vmstate serializationStafford Horne
Previously serialization did not persist the tlb, timer, pic and other key state items. This meant snapshotting and restoring a running os would crash. After adding these I am able to take snapshots of a running linux os and restore at a later time. I am currently not trying to maintain capatibility with older versions as I do not believe this really worked before or anyone used it. Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-05-04target/openrisc: implement shadow registersStafford Horne
Shadow registers are part of the openrisc spec along with sr[cid], as part of the fast context switching feature. When exceptions occur, instead of having to save registers to the stack if enabled the CID will increment and a new set of registers will be available. This patch only implements shadow registers which can be used as extra scratch registers via the mfspr and mtspr if required. This is implemented in a way where it would be easy to add on the fast context switching, currently cid is hardcoded to 0. This is need for openrisc linux smp kernels to boot correctly. Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-05-04target/openrisc: add numcores and coreid supportStafford Horne
These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-05-04target/openrisc: Fixes for memory debuggingStafford Horne
When debugging in gdb you might want to inspect instructions in mapped pages or in exception vectors like 0x800 etc. This was previously not possible in qemu since the *get_phys_page_debug() routine only looked into the data tlb. Change to fall back to look into instruction tlb and plain physical pages. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-04-21target/openrisc: Implement EPH bitTim 'mithro' Ansell
Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-04-21target/openrisc: Implement EVBAR registerTim 'mithro' Ansell
Exception Vector Base Address Register (EVBAR) - This optional register can be used to apply an offset to the exception vector addresses. The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). Its presence is indicated by the EVBARP bit in the CPU Configuration Register (CPUCFGR). Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson
The HW does not special-case r0, but the ABI specifies that r0 should contain 0. If we expose this fact to the optimizer, we can simplify a lot of the generated code. We must of course verify that r0==0, but that is trivial to do with a TB flag. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 18:49:57 +0000