qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2017-12-27	target/*helper: don't check retaddr before calling cpu_restore_state	Alex Bennée
2017-12-18	misc: remove duplicated includes	Philippe Mathieu-Daudé
2017-10-30	Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...	Peter Maydell
2017-10-27	openrisc: cleanup cpu type name composition	Igor Mammedov
2017-10-27	Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging	Peter Maydell
2017-10-25	disas: Remove unused flags arguments	Richard Henderson
2017-10-24	tcg: Initialize cpu_env generically	Richard Henderson
2017-10-24	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota
2017-10-24	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota
2017-10-24	qom: Introduce CPUClass.tcg_initialize	Richard Henderson
2017-10-21	openrisc/cputimer: Perparation for Multicore	Stafford Horne
2017-10-21	target/openrisc: Make coreid and numcores variable	Stafford Horne
2017-10-09	qom/cpu: move cpu_model null check to cpu_class_by_name()	Philippe Mathieu-Daudé
2017-09-06	target: [tcg] Use a generic enum for DISAS_ values	Lluís Vilanova
2017-09-01	openrisc: replace cpu_openrisc_init() with cpu_generic_init()	Igor Mammedov
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne
2017-05-04	target/openrisc: Remove duplicate features property	Stafford Horne
2017-05-04	target/openrisc: Implement full vmstate serialization	Stafford Horne
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne
2017-05-04	target/openrisc: add numcores and coreid support	Stafford Horne
2017-05-04	target/openrisc: Fixes for memory debugging	Stafford Horne
2017-04-21	target/openrisc: Implement EPH bit	Tim 'mithro' Ansell
2017-04-21	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell
2017-02-14	target/openrisc: Optimize for r0 being zero	Richard Henderson
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson
2017-02-14	target/openrisc: Tidy ppc/npc implementation	Richard Henderson
2017-02-14	target/openrisc: Optimize l.jal to next	Richard Henderson
2017-02-14	target/openrisc: Fix madd	Richard Henderson
2017-02-14	target/openrisc: Implement muld, muldu, macu, msbu	Richard Henderson
2017-02-14	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson
2017-02-14	target/openrisc: Implement msync	Richard Henderson
2017-02-14	target/openrisc: Enable trap, csync, msync, psync for user mode	Richard Henderson
2017-02-14	target/openrisc: Set flags on helpers	Richard Henderson
2017-02-14	target/openrisc: Use movcond where appropriate	Richard Henderson
2017-02-14	target/openrisc: Keep SR_CY and SR_OV in a separate variables	Richard Henderson
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson
2017-02-14	target/openrisc: Invert the decoding in dec_calc	Richard Henderson
2017-02-14	target/openrisc: Put SR[OVE] in TB flags	Richard Henderson
2017-02-14	target/openrisc: Streamline arithmetic and OVE	Richard Henderson
2017-02-14	target/openrisc: Rationalize immediate extraction	Richard Henderson
2017-02-14	target/openrisc: Tidy insn dumping	Richard Henderson
2017-02-14	target/openrisc: Implement lwa, swa	Richard Henderson
2017-02-14	target/openrisc: Fix exception handling status registers	Stafford Horne
2017-02-14	target/openrisc: Rename the cpu from or32 to or1k	Richard Henderson
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée
2017-01-13	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée
2017-01-10	target-openrisc: Use clz and ctz opcodes	Richard Henderson
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth