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AgeCommit message (Expand)Author
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson
2019-05-10target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson
2019-05-08target/openrisc: Fix LGPL information in the file headersThomas Huth
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson
2019-04-18disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster
2019-01-30target/openrisc: Fix LGPL version numberThomas Huth
2018-11-27vmstate: constify VMStateFieldMarc-André Lureau
2018-10-31decodetree: Remove "insn" argument from trans_* expandersRichard Henderson
2018-07-03target/openrisc: Fix writes to interrupt mask registerStafford Horne
2018-07-03target/openrisc: Fix delay slot exception flag to match specStafford Horne
2018-07-03linux-user: Implement signals for openriscRichard Henderson
2018-07-03target/openrisc: Reorg tlb lookupRichard Henderson
2018-07-03target/openrisc: Increase the TLB sizeRichard Henderson
2018-07-03target/openrisc: Stub out handle_mmu_fault for softmmuRichard Henderson
2018-07-03target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson
2018-07-03target/openrisc: Fix tlb flushing in mtsprRichard Henderson
2018-07-03target/openrisc: Reduce tlb to a single dimensionRichard Henderson
2018-07-03target/openrisc: Merge mmu_helper.c into mmu.cRichard Henderson
2018-07-03target/openrisc: Remove indirect function calls for mmuRichard Henderson
2018-07-03target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson
2018-07-03target/openrisc: Form the spr index from tcgRichard Henderson
2018-07-03target/openrisc: Exit the TB after l.mtsprRichard Henderson
2018-07-03target/openrisc: Split out is_userRichard Henderson
2018-07-03target/openrisc: Link more translation blocksRichard Henderson
2018-07-03target/openrisc: Fix singlestep_enabledRichard Henderson
2018-07-03target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson
2018-07-03target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson
2018-07-03target/openrisc: Log interruptsRichard Henderson
2018-07-03target/openrisc: Add print_insn_or1kRichard Henderson
2018-07-02target/openrisc: Fix mtspr shadow gprsRichard Henderson
2018-06-04Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into st...Peter Maydell
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
2018-06-01target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé
2018-05-14target/openrisc: Merge disas_openrisc_insnRichard Henderson
2018-05-14target/openrisc: Convert dec_floatRichard Henderson
2018-05-14target/openrisc: Convert dec_compiRichard Henderson
2018-05-14target/openrisc: Convert dec_compRichard Henderson
2018-05-14target/openrisc: Convert dec_MRichard Henderson
2018-05-14target/openrisc: Convert dec_logicRichard Henderson
2018-05-14target/openrisc: Convert dec_macRichard Henderson
2018-05-14target/openrisc: Convert dec_calcRichard Henderson
2018-05-14target/openrisc: Convert remainder of dec_misc insnsRichard Henderson
2018-05-14target/openrisc: Convert memory insnsRichard Henderson
2018-05-14target/openrisc: Convert branch insnsRichard Henderson
2018-05-14target/openrisc: Start conversion to decodetree.pyRichard Henderson
2018-05-14target-openrisc: Write back result before FPE exceptionRichard Henderson
2018-05-09target/openrisc: convert to TranslatorOpsEmilio G. Cota
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