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AgeCommit message (Expand)Author
2019-10-28target/openrisc: fetch code with translator_ldEmilio G. Cota
2019-09-04target/openrisc: Update cpu "any" to v1.3Richard Henderson
2019-09-04target/openrisc: Implement l.adrpRichard Henderson
2019-09-04target/openrisc: Implement move to/from FPCSRRichard Henderson
2019-09-04target/openrisc: Implement unordered fp comparisonsRichard Henderson
2019-09-04target/openrisc: Add support for ORFPX64A32Richard Henderson
2019-09-04target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson
2019-09-04target/openrisc: Fix lf.ftoi.sRichard Henderson
2019-09-04target/openrisc: Add VR2 and AVR special processor registersRichard Henderson
2019-09-04target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson
2019-09-04target/openrisc: Make VR and PPC read-onlyRichard Henderson
2019-09-04target/openrisc: Cache R0 in DisasContextRichard Henderson
2019-09-04target/openrisc: Replace cpu register array with a functionRichard Henderson
2019-09-04target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster
2019-08-16Include hw/boards.h a bit lessMarkus Armbruster
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster
2019-08-16migration: Move the VMStateDescription typedef to typedefs.hMarkus Armbruster
2019-07-05general: Replace global smp variables with smp machine propertiesLike Xu
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster
2019-06-10cpu: Remove CPU_COMMONRichard Henderson
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson
2019-06-10cpu: Introduce cpu_set_cpustate_pointersRichard Henderson
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson
2019-06-10target/openrisc: Use env_cpu, env_archcpuRichard Henderson
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson
2019-06-10cpu: Define ArchCPURichard Henderson
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson
2019-05-10target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson
2019-05-08target/openrisc: Fix LGPL information in the file headersThomas Huth
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson
2019-04-18disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster
2019-01-30target/openrisc: Fix LGPL version numberThomas Huth
2018-11-27vmstate: constify VMStateFieldMarc-André Lureau
2018-10-31decodetree: Remove "insn" argument from trans_* expandersRichard Henderson
2018-07-03target/openrisc: Fix writes to interrupt mask registerStafford Horne
2018-07-03target/openrisc: Fix delay slot exception flag to match specStafford Horne
2018-07-03linux-user: Implement signals for openriscRichard Henderson
2018-07-03target/openrisc: Reorg tlb lookupRichard Henderson
2018-07-03target/openrisc: Increase the TLB sizeRichard Henderson
2018-07-03target/openrisc: Stub out handle_mmu_fault for softmmuRichard Henderson
2018-07-03target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson
2018-07-03target/openrisc: Fix tlb flushing in mtsprRichard Henderson
2018-07-03target/openrisc: Reduce tlb to a single dimensionRichard Henderson