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path: root/target/openrisc/sys_helper.c
AgeCommit message (Expand)Author
2019-01-30target/openrisc: Fix LGPL version numberThomas Huth
2018-07-03target/openrisc: Fix writes to interrupt mask registerStafford Horne
2018-07-03target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson
2018-07-03target/openrisc: Fix tlb flushing in mtsprRichard Henderson
2018-07-03target/openrisc: Reduce tlb to a single dimensionRichard Henderson
2018-07-03target/openrisc: Remove indirect function calls for mmuRichard Henderson
2018-07-03target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson
2018-07-03target/openrisc: Form the spr index from tcgRichard Henderson
2018-07-02target/openrisc: Fix mtspr shadow gprsRichard Henderson
2018-04-11icount: fix cpu_restore_state_from_tb for non-tb-exit casesPavel Dovgalyuk
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne
2017-10-21target/openrisc: Make coreid and numcores variableStafford Horne
2017-05-04target/openrisc: Support non-busy idle state using PMR SPRStafford Horne
2017-05-04target/openrisc: implement shadow registersStafford Horne
2017-05-04target/openrisc: add numcores and coreid supportStafford Horne
2017-04-21target/openrisc: Implement EVBAR registerTim 'mithro' Ansell
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson
2017-02-14target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson
2017-02-14target/openrisc: Keep SR_F in a separate variableRichard Henderson
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée
2016-12-20Move target-* CPU file into a target/ folderThomas Huth