Age | Commit message (Expand) | Author |
---|---|---|
2018-07-03 | target/openrisc: Reorg tlb lookup | Richard Henderson |
2018-07-03 | target/openrisc: Stub out handle_mmu_fault for softmmu | Richard Henderson |
2018-07-03 | target/openrisc: Use identical sizes for ITLB and DTLB | Richard Henderson |
2018-07-03 | target/openrisc: Fix cpu_mmu_index | Richard Henderson |
2018-07-03 | target/openrisc: Reduce tlb to a single dimension | Richard Henderson |
2018-07-03 | target/openrisc: Merge mmu_helper.c into mmu.c | Richard Henderson |
2018-07-03 | target/openrisc: Remove indirect function calls for mmu | Richard Henderson |
2018-07-03 | target/openrisc: Merge tlb allocation into CPUOpenRISCState | Richard Henderson |
2018-01-25 | accel/tcg: add size paremeter in tlb_fill() | Laurent Vivier |
2017-05-04 | target/openrisc: Fixes for memory debugging | Stafford Horne |
2017-02-14 | target/openrisc: Implement lwa, swa | Richard Henderson |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |