qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2019-05-10	target/openrisc: Convert to CPUClass::tlb_fill	Richard Henderson
2019-05-08	target/openrisc: Fix LGPL information in the file headers	Thomas Huth
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster
2018-07-03	target/openrisc: Reorg tlb lookup	Richard Henderson
2018-07-03	target/openrisc: Increase the TLB size	Richard Henderson
2018-07-03	target/openrisc: Use identical sizes for ITLB and DTLB	Richard Henderson
2018-07-03	target/openrisc: Fix cpu_mmu_index	Richard Henderson
2018-07-03	target/openrisc: Reduce tlb to a single dimension	Richard Henderson
2018-07-03	target/openrisc: Remove indirect function calls for mmu	Richard Henderson
2018-07-03	target/openrisc: Merge tlb allocation into CPUOpenRISCState	Richard Henderson
2018-07-03	target/openrisc: Add print_insn_or1k	Richard Henderson
2018-03-19	cpu: get rid of unused cpu_init() defines	Igor Mammedov
2018-03-19	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier
2017-10-27	openrisc: cleanup cpu type name composition	Igor Mammedov
2017-10-21	openrisc/cputimer: Perparation for Multicore	Stafford Horne
2017-09-01	openrisc: replace cpu_openrisc_init() with cpu_generic_init()	Igor Mammedov
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne
2017-05-04	target/openrisc: Remove duplicate features property	Stafford Horne
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne
2017-04-21	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell
2017-02-14	target/openrisc: Optimize for r0 being zero	Richard Henderson
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson
2017-02-14	target/openrisc: Tidy ppc/npc implementation	Richard Henderson
2017-02-14	target/openrisc: Fix madd	Richard Henderson
2017-02-14	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson
2017-02-14	target/openrisc: Keep SR_CY and SR_OV in a separate variables	Richard Henderson
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson
2017-02-14	target/openrisc: Put SR[OVE] in TB flags	Richard Henderson
2017-02-14	target/openrisc: Implement lwa, swa	Richard Henderson
2017-02-14	target/openrisc: Rename the cpu from or32 to or1k	Richard Henderson
2017-01-13	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth