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AgeCommit message (Expand)Author
2017-09-21mips: Improve macro parenthesizationEric Blake
2017-09-21mips: replace cpu_mips_init() with cpu_generic_init()Igor Mammedov
2017-09-21mips: MIPSCPU model subclassesIgor Mammedov
2017-09-21mips: call cpu_mips_realize_env() from mips_cpu_realizefn()Philippe Mathieu-Daudé
2017-09-21mips: split cpu_mips_realize_env() out of cpu_mips_init()Philippe Mathieu-Daudé
2017-09-21mips: introduce internal.h and cleanup cpu.hPhilippe Mathieu-Daudé
2017-09-21mips: move hw/mips/cputimer.c to target/mips/Philippe Mathieu-Daudé
2017-09-19target/mips: Convert VM clock update prints to warn_reportAlistair Francis
2017-09-19Convert single line fprintf(.../n) to warn_report()Alistair Francis
2017-08-02target/mips: Fix RDHWR CC with icountJames Hogan
2017-08-02target/mips: Drop redundant gen_io_start/stop()James Hogan
2017-08-02target/mips: Use BS_EXCP where interrupts are expectedJames Hogan
2017-08-02target-mips: apply CP0.PageMask before writing into TLB entryLeon Alrae
2017-08-02mips: Add KVM T&E segment support for TCGJames Hogan
2017-08-02mips: Improve segment defs for KVM T&E guestsJames Hogan
2017-08-02target-mips: Don't stop on [d]mtc0 DESAVE/KScratchJames Hogan
2017-07-31docs: fix broken paths to docs/devel/tracing.txtPhilippe Mathieu-Daudé
2017-07-21target/mips: Enable CP0_EBase.WG on MIPS64 CPUsJames Hogan
2017-07-21target/mips: Add EVA support to P5600James Hogan
2017-07-20target/mips: Implement segmentation controlJames Hogan
2017-07-20target/mips: Add segmentation control registersJames Hogan
2017-07-20target/mips: Add an MMU mode for ERLJames Hogan
2017-07-20target/mips: Abstract mmu_idx from hflagsJames Hogan
2017-07-20target/mips: Check memory permissions with mem_idxJames Hogan
2017-07-20target/mips: Decode microMIPS EVA load & store instructionsJames Hogan
2017-07-20target/mips: Decode MIPS32 EVA load & store instructionsJames Hogan
2017-07-20target/mips: Prepare loads/stores for EVAJames Hogan
2017-07-20target/mips: Add CP0_Ebase.WG (write gate) supportJames Hogan
2017-07-20target/mips: Weaken TLB flush on UX,SX,KX,ASID changesJames Hogan
2017-07-20target/mips: Fix TLBWI shadow flush for EHINV,XI,RIJames Hogan
2017-07-20target/mips: Fix MIPS64 MFC0 UserLocal on BE hostJames Hogan
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
2017-07-17target/mips: optimize WSBH, DSBH and DSHDAurelien Jarno
2017-07-17mips: set CP0 Debug DExcCode for SDBBP instructionPavel Dovgalyuk
2017-07-11target/mips: fix msa copy_[s|u]_df rd = 0 corner caseMiodrag Dinic
2017-07-04vcpu_dirty: share the same field in CPUState for all acceleratorsSergio Andres Gomez Del Real
2017-06-05target/mips: optimize indirect branchesAurelien Jarno
2017-06-05target/mips: optimize cross-page direct jumps in softmmuAurelien Jarno
2017-03-20target/mips: fix delay slot detection in gen_msa_branch()Yongbok Kim
2017-03-20target-mips: replace few LOG_DISAS() with trace pointsPhilippe Mathieu-Daudé
2017-03-20target-mips: replace break by goto cp0_unimplementedPhilippe Mathieu-Daudé
2017-03-20target-mips: log bad coprocessor0 register accesses with LOG_UNIMPPhilippe Mathieu-Daudé
2017-03-20target-mips: remove old & unuseful commentsPhilippe Mathieu-Daudé
2017-03-20target-mips: fix compiler warnings (clang 5)Philippe Mathieu-Daudé
2017-03-09target/mips: hold BQL for timer interruptsYongbok Kim
2017-03-03KVM: do not use sigtimedwait to catch SIGBUSPaolo Bonzini
2017-03-03KVM: remove kvm_arch_on_sigbusPaolo Bonzini
2017-02-21target-mips: Provide function to test if a CPU supports an ISAPaul Burton
2017-01-24migration: extend VMStateInfoJianjun Duan
2017-01-20Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell