Age | Commit message (Expand) | Author |
---|---|---|
2019-02-14 | target/mips: reimplement SC instruction emulation and use cmpxchg | Leon Alrae |
2019-01-18 | target/mips: Provide R/W access to SAARI and SAAR CP0 registers | Yongbok Kim |
2018-10-18 | target/mips: Add CP0 PWCtl register | Yongbok Kim |
2018-10-18 | target/mips: Add CP0 PWSize register | Yongbok Kim |
2018-10-18 | target/mips: Add CP0 PWField register | Yongbok Kim |
2018-08-24 | target/mips: Implement emulation of nanoMIPS ROTX instruction | Matthew Fortune |
2017-07-20 | target/mips: Add segmentation control registers | James Hogan |
2017-01-10 | target-mips: Use clz opcode | Richard Henderson |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |