Age | Commit message (Expand) | Author |
---|---|---|
2018-01-25 | accel/tcg: add size paremeter in tlb_fill() | Laurent Vivier |
2017-09-21 | mips: introduce internal.h and cleanup cpu.h | Philippe Mathieu-Daudé |
2017-08-02 | mips: Add KVM T&E segment support for TCG | James Hogan |
2017-08-02 | mips: Improve segment defs for KVM T&E guests | James Hogan |
2017-07-20 | target/mips: Implement segmentation control | James Hogan |
2017-07-20 | target/mips: Check memory permissions with mem_idx | James Hogan |
2017-07-20 | target/mips: Add CP0_Ebase.WG (write gate) support | James Hogan |
2017-07-20 | target/mips: Weaken TLB flush on UX,SX,KX,ASID changes | James Hogan |
2017-07-17 | mips: set CP0 Debug DExcCode for SDBBP instruction | Pavel Dovgalyuk |
2017-03-20 | target-mips: fix compiler warnings (clang 5) | Philippe Mathieu-Daudé |
2017-01-13 | cputlb: drop flush_global flag from tlb_flush | Alex Bennée |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |