qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster
2019-02-14	target/mips: introduce MTTCG-enabled builds	Aleksandar Markovic
2019-02-14	target/mips: reimplement SC instruction emulation and use cmpxchg	Leon Alrae
2019-02-14	target/mips: compare virtual addresses in LL/SC sequence	Leon Alrae
2019-01-24	target/mips: Correct the second argument type of cpu_supports_isa()	Aleksandar Markovic
2019-01-18	target/mips: Introduce 32 R5900 multimedia registers	Fredrik Noring
2019-01-18	target/mips: Add CP0 register MemoryMapID	Aleksandar Markovic
2019-01-18	target/mips: Amend preprocessor constants for CP0 registers	Aleksandar Markovic
2019-01-18	target/mips: Update ITU to utilize SAARI and SAAR CP0 registers	Yongbok Kim
2019-01-18	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	Yongbok Kim
2019-01-18	target/mips: Add fields for SAARI and SAAR CP0 registers	Yongbok Kim
2019-01-18	target/mips: Add preprocessor constants for 32 major CP0 registers	Aleksandar Markovic
2019-01-18	target/mips: Move comment containing summary of CP0 registers	Aleksandar Markovic
2018-10-29	target/mips: Introduce MXU registers	Craig Janeczek
2018-10-18	target/mips: Add CP0 PWCtl register	Yongbok Kim
2018-10-18	target/mips: Add CP0 PWSize register	Yongbok Kim
2018-10-18	target/mips: Add CP0 PWField register	Yongbok Kim
2018-10-18	target/mips: Add CP0 PWBase register	Yongbok Kim
2018-10-18	target/mips: Improve DSP R2/R3-related naming	Stefan Markovic
2018-10-18	target/mips: Add bit definitions for DSP R3 ASE	Stefan Markovic
2018-10-18	target/mips: Increase 'supported ISAs/ASEs' flag holder size	Philippe Mathieu-Daudé
2018-10-18	target/mips: Add a comment before each CP0 register section in cpu.h	Aleksandar Markovic
2018-10-18	target/mips: Add a comment with an overview of CP0 registers	Aleksandar Markovic
2018-08-24	target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair	Aleksandar Rikalo
2018-08-16	target/mips: Add CP0 BadInstrX register	Stefan Markovic
2018-08-16	target/mips: Update some CP0 registers bit definitions	Aleksandar Markovic
2018-03-19	cpu: get rid of unused cpu_init() defines	Igor Mammedov
2018-03-19	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov
2017-10-27	mips: malta/boston: replace cpu_model with cpu_type	Igor Mammedov
2017-09-21	mips: replace cpu_mips_init() with cpu_generic_init()	Igor Mammedov
2017-09-21	mips: introduce internal.h and cleanup cpu.h	Philippe Mathieu-Daudé
2017-07-20	target/mips: Add segmentation control registers	James Hogan
2017-07-20	target/mips: Add an MMU mode for ERL	James Hogan
2017-07-20	target/mips: Abstract mmu_idx from hflags	James Hogan
2017-07-20	target/mips: Add CP0_Ebase.WG (write gate) support	James Hogan
2017-02-21	target-mips: Provide function to test if a CPU supports an ISA	Paul Burton
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée
2017-01-13	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth