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2021-11-02target/m68k: Make m68k_cpu_tlb_fill sysemu onlyRichard Henderson
The fallback code in cpu_loop_exit_sigsegv is sufficient for m68k linux-user. Remove the code from cpu_loop that handled EXCP_ACCESS. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/m68k: Drop checks for singlestep_enabledRichard Henderson
GDB single-stepping is now handled generically. Acked-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-13accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.hRichard Henderson
The previous placement in tcg/tcg.h was not logical. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson
We're about to move this out of tcg.h, so rename it as we did when moving MemOp. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson
There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-16Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/linux-user-for-6.2-pull-request' into staging Pull request linux-user 20210916 Code cleanup # gpg: Signature made Thu 16 Sep 2021 16:11:58 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-6.2-pull-request: linux-user: Check lock_user result for ip_mreq_source sockopts linux-user: Drop unneeded includes from qemu.h linux-user: Don't include gdbstub.h in qemu.h linux-user: Split linux-user internals out of qemu.h linux-user: Split safe-syscall macro into its own header linux-user: Split mmap prototypes into user-mmap.h linux-user: Split loader-related prototypes into loader.h linux-user: Split signal-related prototypes into signal-common.h linux-user: Split strace prototypes into strace.h linux-user: Fix coding style nits in qemu.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-14target/m68k: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210911165434.531552-13-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-13linux-user: Don't include gdbstub.h in qemu.hPeter Maydell
Currently the linux-user qemu.h pulls in gdbstub.h. There's no real reason why it should do this; include it directly from the C files which require it, and drop the include line in qemu.h. (Note that several of the C files previously relying on this indirect include were going out of their way to only include gdbstub.h conditionally on not CONFIG_USER_ONLY!) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210908154405.15417-9-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson
The hook is now unused, with breakpoints checked outside translation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21tcg: Rename helper_atomic_*_mmu and provide for user-onlyRichard Henderson
Always provide the atomic interface using TCGMemOpIdx oi and uintptr_t retaddr. Rename from helper_* to cpu_* so as to (mostly) match the exec/cpu_ldst.h functions, and to emphasize that they are not callable from TCG directly. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' ↵Peter Maydell
into staging Add translator_use_goto_tb. Cleanups in prep of breakpoint fixes. Misc fixes. # gpg: Signature made Sat 10 Jul 2021 16:29:14 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210710: (41 commits) cpu: Add breakpoint tracepoints tcg: Remove TCG_TARGET_HAS_goto_ptr accel/tcg: Log tb->cflags with -d exec accel/tcg: Split out log_cpu_exec accel/tcg: Move tb_lookup to cpu-exec.c accel/tcg: Move helper_lookup_tb_ptr to cpu-exec.c target/i386: Use cpu_breakpoint_test in breakpoint_handler tcg: Fix prologue disassembly target/xtensa: Use translator_use_goto_tb target/tricore: Use tcg_gen_lookup_and_goto_ptr target/tricore: Use translator_use_goto_tb target/sparc: Use translator_use_goto_tb target/sh4: Use translator_use_goto_tb target/s390x: Remove use_exit_tb target/s390x: Use translator_use_goto_tb target/rx: Use translator_use_goto_tb target/riscv: Use translator_use_goto_tb target/ppc: Use translator_use_goto_tb target/openrisc: Use translator_use_goto_tb target/nios2: Use translator_use_goto_tb ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-09target/m68k: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Acked-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé
The root trace-events only declares a single TCG event: $ git grep -w tcg trace-events trace-events:115:# tcg/tcg-op.c trace-events:137:vcpu tcg guest_mem_before(TCGv vaddr, uint16_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d" and only a tcg/tcg-op.c uses it: $ git grep -l trace_guest_mem_before_tcg tcg/tcg-op.c therefore it is pointless to include "trace-tcg.h" in each target (because it is not used). Remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210629050935.2570721-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé
Add a target-specific Kconfig. We need the definitions in Kconfig so the minikconf tool can verify they exits. However CONFIG_FOO is only enabled for target foo via the meson.build rules. Two architecture have a particularity, ARM and MIPS. As their translators have been split you can potentially build a plain 32 bit build along with a 64-bit version including the 32-bit subset. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210131111316.232778-6-f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210707131744.26027-2-alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-19tcg: Combine dh_is_64bit and dh_is_signed to dh_typecodeRichard Henderson
We will shortly be interested in distinguishing pointers from integers in the helper's declaration, as well as a true void return. We currently have two parallel 1 bit fields; merge them and expand to a 3 bit field. Our current maximum is 7 helper arguments, plus the return makes 8 * 3 = 24 bits used within the uint32_t typemask. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Introduce Floatx80RoundPrecRichard Henderson
Use an enumeration instead of raw 32/64/80 values. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-28Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' ↵Peter Maydell
into staging Adjust types for some memory access functions. Reduce inclusion of tcg headers. Fix watchpoints vs replay. Fix tcg/aarch64 roli expansion. Introduce SysemuCPUOps structure. # gpg: Signature made Thu 27 May 2021 00:43:54 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210526: (31 commits) hw/core: Constify TCGCPUOps target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps cpu: Move CPUClass::write_elf* to SysemuCPUOps cpu: Move CPUClass::get_crash_info to SysemuCPUOps cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps cpu: Move CPUClass::vmsd to SysemuCPUOps cpu: Introduce SysemuCPUOps structure cpu: Move AVR target vmsd field from CPUClass to DeviceClass cpu: Rename CPUClass vmsd -> legacy_vmsd cpu: Assert DeviceClass::vmsd is NULL on user emulation cpu: Directly use get_memory_mapping() fallback handlers in place cpu: Directly use get_paging_enabled() fallback handlers in place cpu: Directly use cpu_write_elf*() fallback handlers in place cpu: Introduce cpu_virtio_is_big_endian() cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs cpu: Split as cpu-common / cpu-sysemu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson
We no longer have any runtime modifications to this struct, so declare them all const. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org>
2021-05-26cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-21-f4bug@amsat.org> [rth: Drop declaration movement from target/*/cpu.h] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé
Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-15-f4bug@amsat.org> [rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26target/m68k: implement m68k "any instruction" trace modeMark Cave-Ayland
The m68k trace mode is controlled by the top 2 bits in the SR register. Implement the m68k "any instruction" trace mode where bit T1=1 and bit T0=0 in which the CPU generates an EXCP_TRACE exception (vector 9 or offset 0x24) after executing each instruction. This functionality is used by the NetBSD kernel debugger to allow single-stepping on m68k architectures. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210519142917.16693-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-26target/m68k: introduce gen_singlestep_exception() functionMark Cave-Ayland
Introduce a new gen_singlestep_exception() function to be called when generating the EXCP_DEBUG exception in single-step mode rather than calling gen_raise_exception(EXCP_DEBUG) directly. This allows for the single-step exception behaviour for all callers to be managed in a single place. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210519142917.16693-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-26target/m68k: call gen_raise_exception() directly if single-stepping in ↵Mark Cave-Ayland
gen_jmp_tb() In order to consolidate the single-step exception handling into a single helper, change gen_jmp_tb() so that it calls gen_raise_exception() directly instead of gen_exception(). This ensures that all single-step exceptions are now handled directly by gen_raise_exception(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210519142917.16693-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-26target/m68k: introduce is_singlestepping() functionMark Cave-Ayland
The m68k translator currently checks the DisasContextBase singlestep_enabled boolean directly to determine whether to single-step execution. Soon single-stepping may also be triggered by setting the appropriate bits in the SR register so centralise the check into a single is_singlestepping() function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210519142917.16693-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-12Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' ↵Peter Maydell
into staging Prepare MacOS ROM support: - add RTR instruction - fix unaligned access requirement - fix ATC bit (68040 MMU) # gpg: Signature made Thu 11 Mar 2021 22:18:11 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-6.0-pull-request: target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature target/m68k: reformat m68k_features enum target/m68k: don't set SSW ATC bit for physical bus errors target/m68k: implement rtr instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-11target/m68k: add M68K_FEATURE_UNALIGNED_DATA featureMark Cave-Ayland
According to the M68040UM Appendix D the requirement for data accesses to be word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the 68020 onwards will allow unaligned data accesses but at the cost of being less efficient. Add a new M68K_FEATURE_UNALIGNED_DATA feature to specify that data accesses are not required to be word aligned, and don't perform the alignment on the stack pointer when taking an exception if this feature is not selected. This is required because the MacOS DAFB driver attempts to call an A-trap with a byte-aligned stack pointer during initialisation and without this the stack pointer is off by one when the A-trap returns. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210308121155.2476-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-11target/m68k: reformat m68k_features enumMark Cave-Ayland
Move the feature comment from after the feature name to the preceding line to allow for longer feature names and descriptions without hitting the 80 character line limit. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210308121155.2476-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-11target/m68k: don't set SSW ATC bit for physical bus errorsMark Cave-Ayland
If a NuBus slot doesn't contain a card, the Quadra hardware generates a physical bus error if the CPU attempts to access the slot address space. Both Linux and MacOS use a separate bus error handler during NuBus accesses in order to detect and recover when addressing empty slots. According to the MC68040 users manual the ATC bit of the SSW is used to distinguish between ATC faults and physical bus errors. MacOS specifically checks the stack frame generated by a NuBus error and panics if the SSW ATC bit is set. Update m68k_cpu_transaction_failed() so that the SSW ATC bit is not set if the memory API returns MEMTX_DECODE_ERROR which will be used to indicate that an access to an empty NuBus slot occurred. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210308121155.2476-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-11target/m68k: implement rtr instructionLaurent Vivier
This is needed to boot MacOS ROM. Pull the condition code and the program counter from the stack. Operation: (SP) -> CCR SP + 2 -> SP (SP) -> PC SP + 4 -> SP This operation is not privileged. Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210307212552.523552-1-laurent@vivier.eu>
2021-03-11Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging Pull request # gpg: Signature made Wed 10 Mar 2021 21:56:09 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.0-pull-request: (22 commits) sysemu: Let VMChangeStateHandler take boolean 'running' argument sysemu/runstate: Let runstate_is_running() return bool hw/lm32/Kconfig: Have MILKYMIST select LM32_DEVICES hw/lm32/Kconfig: Rename CONFIG_LM32 -> CONFIG_LM32_DEVICES hw/lm32/Kconfig: Introduce CONFIG_LM32_EVR for lm32-evr/uclinux boards qemu-common.h: Update copyright string to 2021 tests/fp/fp-test: Replace the word 'blacklist' qemu-options: Replace the word 'blacklist' seccomp: Replace the word 'blacklist' scripts/tracetool: Replace the word 'whitelist' ui: Replace the word 'whitelist' virtio-gpu: Adjust code space style exec/memory: Use struct Object typedef fuzz-test: remove unneccessary debugging flags net: Use id_generate() in the network subsystem, too MAINTAINERS: Fix the location of tools manuals vhost_user_gpu: Drop dead check for g_malloc() failure backends/dbus-vmstate: Fix short read error handling target/hexagon/gen_tcg_funcs: Fix a typo hw/elf_ops: Fix a typo ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé
We want to move the semihosting code out of hw/ in the next patch. This patch contains the mechanical steps, created using: $ git mv include/hw/semihosting/ include/ $ sed -i s,hw/semihosting,semihosting, $(git grep -l hw/semihosting) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210226131356.3964782-2-f4bug@amsat.org> Message-Id: <20210305135451.15427-2-alex.bennee@linaro.org>
2021-03-09Various spelling fixesMichael Tokarev
An assorted set of spelling fixes in various places. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210309111510.79495-1-mjt@msgid.tls.msk.ru> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-15target/m68k: Drop use of gdb_get_float64() and ldfq_p()Peter Maydell
We used to make a distinction between 'float64'/'float32' types and the 'uint64_t'/'uint32_t' types, requiring special conversion operations to go between them. We've now dropped this distinction as unnecessary, and the 'float*' types remain primarily for documentation purposes when used in places like the function prototypes of TCG helper functions. This means that there's no need for a special gdb_get_float64() function to write a float64 value to the GDB protocol buffer; we can just use gdb_get_reg64(). Similarly, for reading a value out of the GDB buffer into a float64 we can use ldq_p() and need not use ldfq_p(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210208113428.7181-3-peter.maydell@linaro.org> Message-Id: <20210211122750.22645-12-alex.bennee@linaro.org>
2021-02-11m68k: add MSP detection support for stack pointer swap helpersLucien Murray-Pitts
On m68k there are two varities of stack pointers: USP with SSP or ISP/MSP. Only the 68020/30/40 support the MSP register the stack swap helpers don't support this feature. This patch adds this support, as well as comments to CPUM68KState to make it clear how stacks are handled Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <c61ad2d8b39f3b03b431819b6bf602a1c332b921.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: MOVEC insn. should generate exception if wrong CR is accessedLucien Murray-Pitts
Add CPU class detection for each CR type in the m68k_move_to/from helpers, so that it throws and exception if an unsupported register is requested for that CPU class. Reclassified MOVEC insn. as only supported from 68010. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <fc0d0187478716f05d990949347071969b743151.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to ↵Lucien Murray-Pitts
m68k_move_to/from The BUSCR/PCR CR defines were missing for 68060, and the move_to/from helper functions were also missing a decode for the 68060 M68K_CR_CAAR CR register. Added missing defines, and respective decodes for all three CR registers to the helpers. Although this patch defines them, the implementation is empty in this patch and these registers will result in a cpu abort - which is the default prior to this patch. This patch aims to reach full coverage of all CR registers within the helpers. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <19e5c0fa8baed6479ed0502fd3deb132d19457fb.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: improve comments on m68k_move_to/from helpersLucien Murray-Pitts
Add more detailed comments to each case of m68k_move_to/from helpers to list the supported CPUs for that CR as they were wrong in some cases, and missing some cpu classes in other cases. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <a8bd70b66e3dbdb7d2ab7a852af71cdbf341d50c.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: cascade m68k_features by m680xx_cpu_initfn() to improve readabilityLucien Murray-Pitts
The m680XX_cpu_initfn functions have been rearranged to cascade starting from the base 68000, so that the 68010 then inherits from this, and so on until the 68060. This makes it simpler to track features since in most cases the m68k were product enhancements on each other, with only a few instructions being retired. Because each cpu class inherits the previous CPU class, then for example the 68020 also has the feature 68010, and 68000 and so on upto the 68060. - Added 68010 cpu class, and moved correct features into 68000/68010. - Added m68k_unset_feature to allow removing a feature in the inheritence Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <c652fe7537f8b4fe87a13ecbbc0ea751fb71532f.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: improve cpu instantiation commentsLucien Murray-Pitts
Improvement in comments for the instantiation functions. This is to highlight what each cpu class, in the 68000 series, contains in terms of instructions/features. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <2dfe32672ee6ddce4b54c6bcfce579d35abeaf51.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana
we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations into a separate header file, which is only included by TCG, target-specific code. This leaves just a NULL pointer in the cpu.h for the non-TCG builds. This also tidies up the code in all targets a bit, having all TCG cpu operations neatly contained by a dedicated data struct. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-16-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY] avoiding its use in headers used by common_ss code (should be poisoned). Note: need to be careful with the use of CONFIG_USER_ONLY, Message-Id: <20210204163931.7358-11-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-10-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost
[claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-7-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-6-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost
The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an embedded struct for now, to make code conversion easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: move TCGCpuOperations inside include/hw/core/cpu.h] Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-2-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-18gdbstub: drop CPUEnv from gdb_exit()Alex Bennée
gdb_exit() has never needed anything from env and I doubt we are going to start now. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-8-alex.bennee@linaro.org>
2020-12-12m68k: fix some comment spelling errorszhaolichang
I found that there are many spelling errors in the comments of qemu/target/m68k. I used spellcheck to check the spelling errors and found some errors in the folder. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daude<f4bug@amsat.org> Reviewed-by: Laurent Vivier<laurent@vivier.eu> Message-Id: <20201009064449.2336-9-zhaolichang@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-12target/m68k: Add vmstate definition for M68kCPULaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201022203000.1922749-3-laurent@vivier.eu>
2020-12-12target/m68k: remove useless qregs arrayLaurent Vivier
They are unused since the target has been converted to TCG. Fixes: e1f3808e03f7 ("Convert m68k target to TCG.") Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201022203000.1922749-2-laurent@vivier.eu>
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