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2017-01-16Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1' into staging This is the same as the v3 posted except a re-base and a few extra signoffs # gpg: Signature made Fri 13 Jan 2017 14:26:46 GMT # gpg: using RSA key 0xFBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1: cputlb: drop flush_global flag from tlb_flush cpu_common_reset: wrap TCG specific code in tcg_enabled() qom/cpu: move tlb_flush to cpu_common_reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-14target-m68k: increment/decrement with SPLaurent Vivier
On 680x0 family only. Address Register indirect With postincrement: When using the stack pointer (A7) with byte size data, the register is incremented by two. Address Register indirect With predecrement: When using the stack pointer (A7) with byte size data, the register is decremented by two. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-6-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: CAS doesn't need aligned accessLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-5-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: manage pre-dec et post-inc in CASLaurent Vivier
In these cases we must update the address register after the operation. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-4-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: fix gen_flush_flags()Laurent Vivier
gen_flush_flags() is setting unconditionally cc_op_synced to 1 and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set to something else by a previous tcg fragment. We fix that by not setting cc_op_synced to 1 (except for gen_helper_flush_flags() that updates env->cc_op) FIX: https://github.com/vivier/qemu-m68k/issues/19 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-3-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: fix bit operation with immediate valueLaurent Vivier
M680x0 bit operations with an immediate value use 9 bits of the 16bit value, while coldfire ones use only 8 bits. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-2-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: Implement bfffoRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1479242669-25852-1-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14target-m68k: Implement bitfield ops for memoryRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-6-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14target-m68k: Implement bitfield ops for registersRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-5-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée
It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
2016-12-27target-m68k: free TCG variables that are notLaurent Vivier
This is a cleanup patch. It adds call to tcg_temp_free() when it is missing. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: add rol/ror/roxl/roxr instructionsLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: Inline shiftsRichard Henderson
Also manage word and byte operands and fix the computation of overflow in the case of M68000 arithmetic shifts. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-4-git-send-email-rth@twiddle.net>
2016-12-27target-m68k: Do not cpu_abort on undefined insnsRichard Henderson
Report this properly via exception and, importantly, allow the disassembler the chance to tell us what insn is not handled. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-3-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-12-27target-m68k: Implement 680x0 movemLaurent Vivier
680x0 movem can load/store words and long words and can use more addressing modes. Coldfire can only use long words with (Ax) and (d16,Ax) addressing modes. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-2-git-send-email-rth@twiddle.net>
2016-12-27target-m68k: add cas/cas2 opsLaurent Vivier
Implement CAS using cmpxchg. Implement CAS2 using helper and either cmpxchg when the 32bit addresses are consecutive, or with parallel_cpus+cpu_loop_exit_atomic() otherwise. Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: add abcd/sbcd/nbcdLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: add 680x0 divu/divs variantsLaurent Vivier
Update helper to set the throwing location in case of div-by-0. Cleanup divX.w and add quad word variants of divX.l. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twidle.net> [laurent: modified to clear Z on overflow, as found with risu]
2016-12-27target-m68k: add 64bit mullLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twidle.net>
2016-12-27target-m68k: add cmpmLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1477604609-2206-2-git-send-email-laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-4-git-send-email-rth@twiddle.net>
2016-12-27target-m68k: Split gen_lea and gen_eaRichard Henderson
Provide gen_lea_mode and gen_ea_mode, where the mode can be specified manually, rather than taken from the instruction. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-3-git-send-email-rth@twiddle.net>
2016-12-27target-m68k: Delay autoinc writebackRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-2-git-send-email-rth@twiddle.net>
2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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