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AgeCommit message (Expand)Author
2018-03-02target/arm: Decode aa64 armv8.3 fcmlaRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.3 fcaddRichard Henderson
2018-03-02target/arm: Add ARM_FEATURE_V8_FCMARichard Henderson
2018-03-02target/arm: Enable ARM_FEATURE_V8_RDMRichard Henderson
2018-03-02target/arm: Decode aa32 armv8.1 two reg and a scalarRichard Henderson
2018-03-02target/arm: Decode aa32 armv8.1 three sameRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.1 scalar/vector x indexed elementRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.1 three same extraRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.1 scalar three same extraRichard Henderson
2018-03-02target/arm: Refactor disas_simd_indexed size checksRichard Henderson
2018-03-02target/arm: Refactor disas_simd_indexed decodeRichard Henderson
2018-03-02target/arm: Add ARM_FEATURE_V8_RDMRichard Henderson
2018-03-02target/arm: Add Cortex-M33Peter Maydell
2018-03-02target/arm: Define init-svtor property for the reset secure VTOR valuePeter Maydell
2018-03-02target/arm: Define an IDAU interfacePeter Maydell
2018-03-01target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPUPeter Maydell
2018-03-01arm/translate-a64: add all single op FP16 to handle_fp_1src_halfAlex Bennée
2018-03-01arm/translate-a64: implement simd_scalar_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add all FP16 ops in simd_scalar_pairwiseAlex Bennée
2018-03-01arm/translate-a64: add FP16 FMOV to simd_mod_immAlex Bennée
2018-03-01arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/helper.c: re-factor rsqrte and add rsqrte_f16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FRECPEAlex Bennée
2018-03-01arm/helper.c: re-factor recpe and add recepe_f16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: initial decode for simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée
2018-03-01arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexedAlex Bennée
2018-03-01arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: initial decode for simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: handle_3same_64 comment fixAlex Bennée
2018-03-01arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)Alex Bennée
2018-03-01target/arm/helper: pass explicit fpst to set_rmodeAlex Bennée
2018-03-01target/arm/cpu.h: add additional float_status flagsAlex Bennée
2018-03-01target/arm/cpu.h: update comment for half-precision valuesAlex Bennée
2018-03-01target/arm/cpu64: introduce ARM_V8_FP16 feature bitAlex Bennée
2018-02-22target/arm: Fix register definitions for VMIDR and VMPIDRPeter Maydell
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée
2018-02-15target/arm: Implement v8M MSPLIM and PSPLIM registersPeter Maydell
2018-02-15target/arm: Migrate v7m.other_spPeter Maydell
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