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path: root/target/arm/translate-a64.c
AgeCommit message (Expand)Author
2018-05-15target/arm: Implement FCVT (scalar, fixed-point) for fp16Richard Henderson
2018-05-15target/arm: Implement FCVT (scalar, integer) for fp16Richard Henderson
2018-05-15target/arm: Early exit after unallocated_encoding in disas_fp_int_convRichard Henderson
2018-05-15target/arm: Implement FMOV (general) for fp16Richard Henderson
2018-05-11Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell
2018-05-10target/arm: Clear SVE high bits for FMOVRichard Henderson
2018-05-10target/arm: Fix float16 to/from int16Richard Henderson
2018-05-10target/arm: Implement vector shifted FCVT for fp16Richard Henderson
2018-05-10target/arm: Implement vector shifted SCVF/UCVF for fp16Richard Henderson
2018-05-10target/arm: Implement CAS and CASPRichard Henderson
2018-05-10target/arm: Fill in disas_ldst_atomicRichard Henderson
2018-05-10target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decodeRichard Henderson
2018-05-10target/arm: Use new min/max expandersRichard Henderson
2018-05-09translator: merge max_insns into DisasContextBaseEmilio G. Cota
2018-05-04target/arm: Tidy condition in disas_simd_two_reg_miscRichard Henderson
2018-05-04target/arm: Tidy conditions in handle_vec_simd_shriRichard Henderson
2018-04-26target/arm: Allow EL change hooks to do IOAaron Lindsay
2018-03-23target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRKPeter Maydell
2018-03-23arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXITVictor Kamensky
2018-03-02target/arm: Decode aa64 armv8.3 fcmlaRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.3 fcaddRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.1 scalar/vector x indexed elementRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.1 three same extraRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.1 scalar three same extraRichard Henderson
2018-03-02target/arm: Refactor disas_simd_indexed size checksRichard Henderson
2018-03-02target/arm: Refactor disas_simd_indexed decodeRichard Henderson
2018-03-01arm/translate-a64: add all single op FP16 to handle_fp_1src_halfAlex Bennée
2018-03-01arm/translate-a64: implement simd_scalar_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add all FP16 ops in simd_scalar_pairwiseAlex Bennée
2018-03-01arm/translate-a64: add FP16 FMOV to simd_mod_immAlex Bennée
2018-03-01arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FRECPEAlex Bennée
2018-03-01arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: initial decode for simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée
2018-03-01arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexedAlex Bennée
2018-03-01arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: initial decode for simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: handle_3same_64 comment fixAlex Bennée
2018-03-01arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)Alex Bennée
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