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QEMU is a generic and open source machine & userspace emulator and virtualizer.
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cpu.c
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Author
2017-12-21
cpu: refactor cpu_address_space_init()
Peter Xu
2017-11-09
disas: Dump insn bytes along with capstone disassembly
Richard Henderson
2017-10-27
Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging
Peter Maydell
2017-10-26
tcg: Avoid setting tcg_initialize if !CONFIG_TCG
Richard Henderson
2017-10-25
arm: Support Capstone in disas_set_info
Richard Henderson
2017-10-25
target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLY
Richard Henderson
2017-10-25
target/arm: Move BE32 disassembler fixup
Richard Henderson
2017-10-24
qom: Introduce CPUClass.tcg_initialize
Richard Henderson
2017-10-09
qom/cpu: move cpu_model null check to cpu_class_by_name()
Philippe Mathieu-Daudé
2017-10-06
nvic: Implement Security Attribution Unit registers
Peter Maydell
2017-09-23
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
2017-09-22
memory: Get rid of address_space_init_shareable
Alexey Kardashevskiy
2017-09-21
nvic: Implement AIRCR changes for v8M
Peter Maydell
2017-09-19
arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly
Igor Mammedov
2017-09-14
target/arm: Clear exclusive monitor on v7M reset, exception entry/exit
Peter Maydell
2017-09-07
target/arm: Add Jazelle feature
Portia Stephens
2017-09-07
target/arm: Implement new do_transaction_failed hook
Peter Maydell
2017-09-07
target/arm: Make CCR register banked for v8M
Peter Maydell
2017-09-07
target/arm: Make MPU_RNR register banked for v8M
Peter Maydell
2017-09-07
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Peter Maydell
2017-09-07
target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
Peter Maydell
2017-09-07
target/arm: Register second AddressSpace for secure v8M CPUs
Peter Maydell
2017-09-07
target/arm: Add state field, feature bit and migration for v8M secure state
Peter Maydell
2017-09-07
target/arm: Implement ARMv8M's PMSAv8 registers
Peter Maydell
2017-09-04
hw/arm/virt: add pmu interrupt state
Andrew Jones
2017-09-04
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
Peter Maydell
2017-07-31
target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset
Peter Maydell
2017-07-17
target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions
Peter Maydell
2017-06-06
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...
Peter Maydell
2017-06-05
numa: move numa_node from CPUState into target specific classes
Igor Mammedov
2017-06-04
target/arm: add data cache invalidation cp15 instruction to cortex-r5
Luc MICHEL
2017-06-02
arm: All M profile cores are PMSA
Peter Maydell
2017-06-02
arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
Peter Maydell
2017-06-02
arm: Clean up handling of no-MPU PMSA CPUs
Peter Maydell
2017-06-02
target/arm: clear PMUVER field of AA64DFR0 when vPMU=off
Wei Huang
2017-05-11
virt-arm: add node-id property to CPU
Igor Mammedov
2017-05-11
hw/arm/virt: extract mp-affinity calculation in separate function
Igor Mammedov
2017-04-20
arm: Remove workarounds for old M-profile exception return implementation
Peter Maydell
2017-02-28
armv7m: Fix condition check for taking exceptions
Peter Maydell
2017-02-24
target-arm/powerctl: defer cpu reset work to CPU context
Alex Bennée
2017-02-10
target-arm: Enable vPMU support under TCG mode
Wei Huang
2017-02-07
arm: Correctly handle watchpoints for BE32 CPUs
Julian Brown
2017-02-07
Fix Thumb-1 BE32 execution and disassembly.
Julian Brown
2017-02-07
target/arm: Add cfgend parameter for ARM CPU selection.
Julian Brown
2017-01-27
armv7m: R14 should reset to 0xffffffff
Peter Maydell
2017-01-27
armv7m: FAULTMASK should be 0 on reset
Michael Davidsaver
2017-01-27
armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR
Peter Maydell
2017-01-27
target/arm: Drop IS_M() macro
Peter Maydell
2017-01-27
armv7m: Replace armv7m.hack with unassigned_access handler
Michael Davidsaver
2017-01-20
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
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