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path: root/target-xtensa/translate.c
AgeCommit message (Expand)Author
2012-12-08target-xtensa: implement MISC SRMax Filippov
2012-12-08target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin
2012-11-10target-xtensa: avoid using cpu_single_envBlue Swirl
2012-10-06target-xtensa: de-optimize EXTUIAurelien Jarno
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson
2012-09-22target-xtensa: implement coprocessor context optionMax Filippov
2012-09-22target-xtensa: implement FP1 groupMax Filippov
2012-09-22target-xtensa: implement FP0 conversionsMax Filippov
2012-09-22target-xtensa: implement FP0 arithmeticMax Filippov
2012-09-22target-xtensa: implement LSCX and LSCI groupsMax Filippov
2012-09-22target-xtensa: add FP registersMax Filippov
2012-09-21target-xtensa: don't emit extra tcg_gen_goto_tbMax Filippov
2012-09-21target-xtensa: fix extui shift amountMax Filippov
2012-07-28target-xtensa: fix big-endian BBS/BBC implementationMax Filippov
2012-06-10target-xtensa: switch to AREG0-free modeMax Filippov
2012-06-09target-xtensa: fix CCOUNT for conditional branchesMax Filippov
2012-04-21target-xtensa: fix LOOPNEZ/LOOPGTZ translationMax Filippov
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov
2011-10-15target-xtensa: implement MAC16 optionMax Filippov
2011-09-10target-xtensa: implement boolean optionMax Filippov
2011-09-10target-xtensa: implement memory protection optionsMax Filippov
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov
2011-09-10target-xtensa: implement accurate window checkMax Filippov
2011-09-10target-xtensa: implement interrupt optionMax Filippov
2011-09-10target-xtensa: implement SIMCALLMax Filippov
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov
2011-09-10target-xtensa: implement extended L32RMax Filippov
2011-09-10target-xtensa: implement loop optionMax Filippov
2011-09-10target-xtensa: implement windowed registersMax Filippov
2011-09-10target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov
2011-09-10target-xtensa: implement exceptionsMax Filippov
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