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AgeCommit message (Expand)Author
2014-10-20target-tricore: Add instructions of BO opcode formatBastian Koppelmann
2014-10-20target-tricore: Add instructions of BIT opcode formatBastian Koppelmann
2014-10-20target-tricore: Add instructions of B opcode formatBastian Koppelmann
2014-10-20target-tricore: Add instructions of ABS, ABSB opcode formatBastian Koppelmann
2014-10-20target-tricore: Cleanup and BugfixesBastian Koppelmann
2014-09-25target-tricore: Remove the dummy interrupt boilerplateRichard Henderson
2014-09-01target-tricore: Add instructions of SR opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SLR, SSRO and SRO opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SC opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SBR opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SBC and SBRN opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SB opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SRRS and SLRO opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SSR opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SRR opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SRC opcode formatBastian Koppelmann
2014-09-01target-tricore: Add masks and opcodes for decodingBastian Koppelmann
2014-09-01target-tricore: Add initialization for translation and activate targetBastian Koppelmann
2014-09-01target-tricore: Add softmmu supportBastian Koppelmann
2014-09-01target-tricore: Add target stubs and qom-cpuBastian Koppelmann
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 16:21:32 +0000