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path: root/target-sh4/translate.c
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2011-01-16target-sh4: implement negc using TCGAurelien Jarno
Using setcond it's now possible to generate a relatively short negc instruction in TCG. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-16target-sh4: use rotl/rotr when possibleAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: use setcond when possibleAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: log instructions start in TCG codeAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: simplify comparisons after a 'and' opAurelien Jarno
When a TCG variable is anded with a value and the compared with the same value, we can simply invert the comparison and compare it with 0. The generated code is smaller. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: fix reset on r2dAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: optimize exceptionsAurelien Jarno
As exception is not the normal path, don't bother saving PC, before raising one, instead rely on code retranslation to get the CPU state. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: add ftrv instructionAurelien Jarno
Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column matrix XMTRX by the 4-dimensional vector FVn. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: add fipr instructionAurelien Jarno
Add the fipr FVm,FVn instruction, which computes the inner products of a 4-dimensional single precision floating-point vector. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: implement flush-to-zeroAurelien Jarno
When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers as zero. Enable the corresponding softfloat option when this bit is set. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: define FPSCR constantsAurelien Jarno
Define FPSCR constants for all field and use them instead of hardcoded values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: use default-NaN modeAurelien Jarno
SH4 FPU doesn't propagate NaN, and instead always regenerate new ones. Enable the default-NaN mode by default. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-11target-sh4: fix fpu disabled/illegal exceptionAurelien Jarno
Illegal instructions in a slot delay should generate a slot illegal instruction exception instead of an illegal instruction exception. The current PC should be saved before generating such an exception, but should not be corrected if in a delay slot, given it's already done in the exception handler do_interrupt(). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-12target-sh4: Add support for ldc & stc with sgrAlexandre Courbot
Add support for the following missing priviledged intructions: For SH4: - stc sgr, Rn - stc.l sgr, @-Rn For SH4A: - ldc Rm, sgr - ldc.l @Rm+, sgr Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-12target-sh4: Split the LDST macro into 2 sub-macrosAlexandre Courbot
The LDST macro is used to generate ldc and stc instructions that work with a specific register. However, the SGR register only supports stc up to SH4A, which supports both stc and ldc. This patch creates two sub-macros named LD and ST that handle generating ldc and stc instructions separately, and redeclares LDST to use these sub-macro. Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05target-sh4: Remove duplicate CPU log.Richard Henderson
Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08remove TARGET_* defines from translate-all.cPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09target-sh4: MMU: fix mem_idx computationAurelien Jarno
The mem_idx is wrongly computed. As written in target-sh4/cpu.h, mode 0 corresponds to kernel mode (SR_MD = 1), while mode 1 corresponds to user mode (SR_MD = 0). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08target-sh4: minor optimisationsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-12Fix sys-queue.h conflict for goodBlue Swirl
Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896, f40d753718c72693c5f520f0d9899f6e50395e94, 96555a96d724016e13190b28cffa3bc929ac60dc and 3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-13Include assert.h from qemu-common.hPaul Brook
Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05Add new command line option -singlestep for tcg single stepping.aurel32
This replaces a compile time option for some targets and adds this feature to targets which did not have a compile time option. Add monitor command to enable or disable single step mode. Modify monitor command "info status" to display single step mode. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-01SH: Improve movca.l/ocbi emulation.edgar_igl
Author: Vladimir Prus <vladimir@codesourcery.com> Fix movcal.l/ocbi emulation. * target-sh4/cpu.h (memory_content): New. (CPUSH4State): New fields movcal_backup and movcal_backup_tail. * target-sh4/helper.h (helper_movcal) (helper_discard_movcal_backup, helper_ocbi): New. * target-sh4/op_helper.c (helper_movcal) (helper_discard_movcal_backup, helper_ocbi): New. * target-sh4/translate.c (DisasContext): New field has_movcal. (sh4_defs): Update CVS for SH7785. (cpu_sh4_init): Initialize env->movcal_backup_tail. (_decode_opc): Discard movca.l-backup. Make use of helper_movcal and helper_ocbi. (gen_intermediate_code_internal): Initialize has_movcal to 1. Thanks to Shin-ichiro KAWASAKI and Paul Mundt for valuable feedback. Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6966 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02SH: Implement MOVCO.L and MOVLI.Laurel32
* target-sh4/cpu.h (struct CPUSH4State): New field ldst. * target-sh4/translate.c (cpu_ldst): New. (sh4_translate_init): Initialize cpu_ldst. (_decode_opc): Support MOVCO.L and MOVLI.L. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6666 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-07SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 ↵aurel32
and fix BCR2 support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6548 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26Log reset events (Jan Kiszka)aliguori
Original idea&code by Kevin Wolf, split-up in two patches and added more archs. This patch introduces a flag to log CPU resets. Useful for tracing unexpected resets (such as those triggered by x86 triple faults). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)aliguori
These are references to 'loglevel' that aren't on a simple 'if (loglevel & X) qemu_log()' statement. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15Convert references to logfile/loglevel to use qemu_log*() macrosaliguori
This is a large patch that changes all occurrences of logfile/loglevel global variables to use the new qemu_log*() macros. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14sh4: Add FMAC instruction supportaurel32
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6309 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel32
The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-01tcg_temp_local_new should take no parameteraurel32
This patch removes useless type information in some calls to tcg_temp_local_new. It also removes the parameter from the macro declaration; if a target has to use a specific non-default size then it should use tcg_temp_local_new_{i32,i64}. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6146 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc
Change from v1: Avoid changing the existing coding style in certain files. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13target-sh4: make the initial value of SR easier to readaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6016 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13target-sh4: don't disable FPU instructions in user modeaurel32
Based on a patch from Lionel Landwerlin. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6015 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13target-sh4: disable debug codeaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6014 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13target-sh4: add prefi, icbi, syncoaurel32
(Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6013 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13target-sh4: add SH7785 as CPU optionaurel32
(Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6012 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10target-sh4: check FD bit for FP instructionsaurel32
Based on a patch from Vladimir Prus <vladimir@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5970 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: kill a few warningsaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: Implement FD bitaurel32
SH4 manual say that if a floating point instruction is executed while FD bit in the status register is 1, an exception should be raised. QEMU presently does not do that, so the kernel does not initialize FP state for any thread, nor does it save/restore FP state. The most apparent consequence is that while recent gcc/libc expect double-precision mode to be set by kernel, they run in single-precision mode, and all FP code produces wrong values. This patch fixes this. It also fixes a couple of places where PC was not updated before handling an exception, although both those places deal with invalid instruction and don't lead to any user-visible bugs. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5937 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-25Use sys-queue.h for break/watchpoint managment (Jan Kiszka)aliguori
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the code and also fixing a use after release issue in cpu_break/watchpoint_remove_all. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-22target-sh4: fix 64-bit fmov to/from memoryaurel32
When loading/storing a register pair, the even-numbered register always maps to the low 32 bits of memory independently of target endian configuration. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5773 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-20target-sh4: fix fldi0/fldi1aurel32
fldi0/fldi1 should be executed as a nop if FPSCR.FR is set instead of generating an exception. Reported by Laurent Desnogues. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5759 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-19target-sh4: map FP registers as TCG variablesaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5758 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18Refactor and enhance break/watchpoint API (Jan Kiszka)aliguori
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the succeeding enhancements this series comes with. First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching to dynamically allocated data structures that are kept in linked lists. This also allows to return a stable reference to the related objects, required for later introduced x86 debug register support. Breakpoints and watchpoints are stored with their full information set and an additional flag field that makes them easily extensible for use beyond pure guest debugging. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17TCG variable type checking.pbrook
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
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