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path: root/target-ppc/translate_init.c
AgeCommit message (Expand)Author
2013-01-18PPC: Provide zero SVR for -cpu e500mc and e5500Alexander Graf
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber
2013-01-07target-ppc: Slim conversion of model definitions to QOM subclassesAndreas Färber
2013-01-07PPC: Bring EPR support closer to realityAlexander Graf
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini
2012-12-19exec: move include files to include/exec/Paolo Bonzini
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini
2012-10-29target-ppc: Rework storage of VPA registration stateDavid Gibson
2012-10-29PPC: 440: Emulate DCBR0Alexander Graf
2012-10-05ppc/pseries: Reset VPA registration on CPU resetDavid Gibson
2012-08-15win32: provide separate macros for weak decls and definitionsAnthony Liguori
2012-08-13target-ppc: add implementation of query-cpu-definitions (v2)Anthony Liguori
2012-06-24target-ppc: Fix 2nd parameter for tcg_gen_shri_tlStefan Weil
2012-06-24PPC: BookE: Support 32 and 64 bit wide MAS2Alexander Graf
2012-06-24PPC: Extract SPR dump generation into its own functionAlexander Graf
2012-06-24PPC: Add e5500 CPU targetAlexander Graf
2012-06-24PPC: BookE: Make ivpr selectable by CPU typeAlexander Graf
2012-06-24ppc64: Rudimentary Support for extra page sizes on server CPUsBenjamin Herrenschmidt
2012-06-24ppc: Avoid AREG0 for misc helpersBlue Swirl
2012-06-24ppc: Avoid AREG0 for timebase helpersBlue Swirl
2012-06-24ppc: Avoid AREG0 for MMU etc. helpersBlue Swirl
2012-05-01PPC: Fix up e500 cache size settingAlexander Graf
2012-04-15target-ppc: Init dcache and icache size for e500 user modeMeador Inge
2012-04-15target-ppc: Fix type casts for w64 (uintptr_t)Stefan Weil
2012-04-15target-ppc: QOM'ify CPU resetAndreas Färber
2012-04-15target-ppc: Start QOM'ifying CPU initAndreas Färber
2012-04-15target-ppc: QOM'ify CPUAndreas Färber
2012-04-15target-ppc: Add hooks for handling tcg and kvm limitationsDavid Gibson
2012-04-07Replace Qemu by QEMU in commentsStefan Weil
2012-03-15ppc: Correctly define POWERPC_INSNS2_DEFAULTMeador Inge
2012-03-15PPC: Add PIR register to POWER7 CPUNathan Whitehorn
2012-03-15PPC64: Add support for ldbrx and stdbrx instructionsThomas Huth
2012-03-14target-ppc: Don't overuse CPUStateAndreas Färber
2012-02-02PPC: E500: Populate L1CFG0 SPRAlexander Graf
2012-02-02PPC: e500mc: Enable processor controlAlexander Graf
2012-02-02PPC: e500: msync is 440 only, e500 has real syncAlexander Graf
2012-02-02PPC: e500mc: add missing IVORs to bitmapAlexander Graf
2012-02-02PPC: Add IVOR 38-42Alexander Graf
2012-01-21PPC: Enable 440EP CPU targetAlexander Graf
2012-01-03PPC: Add description for the Freescale e500mc core.Varun Sethi
2011-10-31ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriateDavid Gibson
2011-10-30pseries: Correct vmx/dfp handling in both KVM and TCG casesDavid Gibson
2011-10-30PPC: Disable non-440 CPUs for ppcemb targetAlexander Graf
2011-10-30ppc: Add cpu defs for POWER7 revisions 2.1 and 2.3David Gibson
2011-10-30ppc: First cut implementation of -cpu hostDavid Gibson
2011-10-30ppc: Remove broken partial PVR matchingDavid Gibson
2011-10-06PPC: booke timersFabien Chouteau
2011-10-06Gdbstub: handle read of fpscrFabien Chouteau
2011-10-06Implement POWER7's CFAR in TCGDavid Gibson
2011-08-20Use glib memory allocation and free functionsAnthony Liguori
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