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path: root/target-ppc/translate_init.c
AgeCommit message (Expand)Author
2016-10-24exec: call cpu_exec_exit() from a CPU unrealize common functionLaurent Vivier
2016-10-24exec: move cpu_exec_init() calls to realize functionsLaurent Vivier
2016-09-27linux-user: remove #define smp_{cores, threads}Marc-André Lureau
2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt
2016-09-07target-ppc: introduce opc4 for Expanded OpcodeNikunj A Dadhania
2016-09-07target-ppc: Introduce POWER ISA 3.0 flagNikunj A Dadhania
2016-09-07target-ppc: Introduce Power9 familyAneesh Kumar K.V
2016-08-10ppc: Introduce a function to look up CPU alias stringsThomas Huth
2016-07-25target-ppc: add PPC_MFTB flag to e500mc and e5500Michael Walle
2016-07-18ppc: abort if compat property contains an unknown valueGreg Kurz
2016-07-12Use #include "..." for our own headers, <...> for othersMarkus Armbruster
2016-07-05ppc/hash64: Add proper real mode translation supportBenjamin Herrenschmidt
2016-07-05ppc: simplify max_smt initialization in ppc_cpu_realizefn()Greg Kurz
2016-07-01ppc: Fix 64K pages support in full emulationBenjamin Herrenschmidt
2016-07-01ppc: LPCR is a HV resourceBenjamin Herrenschmidt
2016-07-01ppc: Initial HDEC supportBenjamin Herrenschmidt
2016-07-01ppc: Use a helper to filter writes to LPCRBenjamin Herrenschmidt
2016-07-01ppc: Add a bunch of hypervisor SPRs to Book3sBenjamin Herrenschmidt
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt
2016-06-23ppc: Add real mode CI load/store instructions for P7 and P8Benjamin Herrenschmidt
2016-06-23ppc: Fix POWER7 and POWER8 exception definitionsBenjamin Herrenschmidt
2016-06-23ppc: define a default LPCR valueBenjamin Herrenschmidt
2016-06-22ppc: Improve emulation of THRM registersBenjamin Herrenschmidt
2016-06-14ppc: Add PowerISA 2.07 compatibility modeThomas Huth
2016-06-14ppc: Improve PCR bit selection in ppc_set_compat()Thomas Huth
2016-06-14ppc: Split pcr_mask settings into supported bits and the register maskThomas Huth
2016-06-07ppc: POWER7 has lq/stq instructions and stq need to check ISABenjamin Herrenschmidt
2016-06-07ppc: POWER7 had ACOP and PID registersBenjamin Herrenschmidt
2016-06-07ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt
2016-05-30ppc: Add PPC_64H instruction flag to POWER7 and POWER8Benjamin Herrenschmidt
2016-05-27PPC/KVM: early validation of vcpu idGreg Kurz
2016-05-19ppc: use PowerPCCPU instead of CPUPPCStatePaolo Bonzini
2016-04-05ppc: Rework POWER7 & POWER8 exception modelCédric Le Goater
2016-03-24ppc: move POWER8 Book4 regs in their own routineCédric Le Goater
2016-03-24ppc: A couple more dummy POWER8 Book4 regsBenjamin Herrenschmidt
2016-03-24ppc: Add dummy CIABR SPRBenjamin Herrenschmidt
2016-03-24ppc: Add POWER8 IAMR registerBenjamin Herrenschmidt
2016-03-24ppc: Fix writing to AMR/UAMORBenjamin Herrenschmidt
2016-03-24ppc: Initialize AMOR in PAPR modeBenjamin Herrenschmidt
2016-03-24ppc: Add dummy SPR_IC for POWER8Benjamin Herrenschmidt
2016-03-24ppc: Create cpu_ppc_set_papr() helperBenjamin Herrenschmidt
2016-03-24ppc: Add a bunch of hypervisor SPRs to Book3sBenjamin Herrenschmidt
2016-03-24ppc: Add macros to register hypervisor mode SPRsBenjamin Herrenschmidt
2016-03-24ppc64: set MSR_SF bitLaurent Vivier
2016-03-16target-ppc: Add PVR for POWER8NVL processorAlexey Kardashevskiy
2016-03-16ppc: Add a few more P8 PMU SPRsBenjamin Herrenschmidt
2016-03-16ppc: Fix migration of the TAR SPRThomas Huth
2016-03-16ppc: Define the PSPB register on POWER8Thomas Huth
2016-02-08qom: Swap 'name' next to visitor in ObjectPropertyAccessorEric Blake
2016-02-08qapi: Swap visit_* arguments for consistent 'name' placementEric Blake
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