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AgeCommit message (Expand)Author
2007-12-26De-cruft exception definitions, and implement nicer debug output.ths
2007-12-25Support for VR5432, and some of its special instructions. Original patchths
2007-12-255K and 20K are Release 1 CPUs.ths
2007-12-25Avoid host FPE for overflowing division on MIPS, by Richard Sandiford.ths
2007-12-25Improved PABITS handling, and config register fixes.ths
2007-12-24Update debug code to match new accumulator register layout.ths
2007-12-24Fix CCRes value for 20Kc.ths
2007-12-17MIPS TODO: mention unimplemented system controllers.ths
2007-12-17Update MIPS TODO. The mipsnet failure is caused by a kernel bug.ths
2007-12-09Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.ths
2007-12-02Larger physical address space for 32-bit MIPS.ths
2007-11-26Micro-optimize back-to-back store-load sequences.ths
2007-11-22Optimize the conventional move operation.ths
2007-11-22Fix off-by-one address checks in MIPS64 MMU, by Aurelien Jarno.ths
2007-11-19Add older 4Km variants.ths
2007-11-18Add strict checking mode for softfp code.pbrook
2007-11-18Fix MIPS64 R2 instructions.ths
2007-11-18Use a valid PRid.ths
2007-11-17Fix int/float inconsistencies.pbrook
2007-11-14Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSPths
2007-11-10added cpu_model parameter to cpu_init()bellard
2007-11-09Use FORCE_RET, scrap RETURN which was implemented in target-specific code.ths
2007-11-09Move kernel loader parameters from the cpu state to being board specific.ths
2007-11-08Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths
2007-11-08Formatting fix.ths
2007-10-29Adjust s390 addresses (the MSB is defined as "to be ignored").ths
2007-10-29Preliminary MIPS64R2 mode.ths
2007-10-29Fix logic bug which broke TLBL/TLBS handling somewhat.ths
2007-10-29Restrict CP0_PerfCnt to legal values.ths
2007-10-28Implement missing MIPS supervisor mode bits.ths
2007-10-27Add sharable clz/clo inline functions and use them for the mips target.ths
2007-10-26The other half of the mul64 rework. Sorry for the breakage, I committedths
2007-10-24Remove bogus instruction decode.ths
2007-10-24Force proper sign extension for mfc0/mfhc0 on MIPS64.ths
2007-10-23Fix writable length of the index register.ths
2007-10-23Enforce proper sign extension for lwl/lwr on MIPS64.ths
2007-10-23Fix CLO calculation for MIPS64. And a small code cleanup.ths
2007-10-23Use the standard ASE check for MIPS-3D and MT.ths
2007-10-23Switch bc1any* instructions off if no MIPS-3D is implemented.ths
2007-10-20Handle IBE on MIPS properly.ths
2007-10-17Update TODO.ths
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer
2007-10-13Update TODO.ths
2007-10-13Fix off-by-one in address check.ths
2007-10-12Unify '-cpu ?' option.j_mayer
2007-10-09Use always_inline in the MIPS support where applicable.ths
2007-10-09Delete file which should have been removed in the lst commit.ths
2007-10-09Fix [ls][wd][lr] instructions, by Aurelien Jarno.ths
2007-09-30Code provision for n32/n64 mips userland emulation. Not functional yet.ths
2007-09-30Update TODO.ths