summaryrefslogtreecommitdiff
path: root/target-mips/cpu.h
AgeCommit message (Expand)Author
2008-05-28Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford.ths
2008-05-06Use TCG for MIPS GPR moves.ths
2008-05-04Simplify mips branch handling. Retire T2 from use. Use TCG for branches.ths
2008-02-12Make MIPS MT implementation more cache friendly.ths
2007-12-30MIPS COP1X (and related) instructions, by Richard Sandiford.ths
2007-12-26De-cruft exception definitions, and implement nicer debug output.ths
2007-12-25Improved PABITS handling, and config register fixes.ths
2007-11-10added cpu_model parameter to cpu_init()bellard
2007-11-09Move kernel loader parameters from the cpu state to being board specific.ths
2007-10-28Implement missing MIPS supervisor mode bits.ths
2007-10-20Handle IBE on MIPS properly.ths
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer
2007-10-12Unify '-cpu ?' option.j_mayer
2007-09-27Move get_sp_from_cpustate from cpu.h to target_signal.h.ths
2007-09-27linux-user sigaltstack() syscall, by Thayne Harbaugh.ths
2007-09-25Optimise instructions accessing CP0, by Aurelien Jarno.ths
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths
2007-09-06Partial support for 34K multithreading, not functional yet.ths
2007-06-23Handle MIPS64 SEGBITS value correctly.ths
2007-06-03Move target-specific defines to the target directories.ths
2007-05-31Don't kill the registered irqs on reset.ths
2007-05-30Fix CPU (re-)selection on reset.ths
2007-05-29Fix usermode check, thanks Aurelien Jarno.ths
2007-05-29Don't check the FPU state for each FPU instruction, use hflags toths
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths
2007-05-23The 24k wants more watch and srsmap registers.ths
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths
2007-05-13MIPS linux-user update.ths
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths
2007-04-07Unify IRQ handling.pbrook
2007-04-0564bit MIPS FPUs have 32 registers.ths
2007-03-30Fix typo, suggested by Ben Taylor.ths
2007-03-30Sanitize mips exception handling.ths
2007-03-23Fix enough FPU/R2 support to get 24Kf going.ths
2007-03-18MIPS -cpu selection support, by Herve Poussineau.ths
2007-03-02MIPS Userland TLS register emulation, by Daniel Jacobowitz.ths
2007-02-28MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths
2007-02-20Replace TLSZ with TARGET_FMT_lx.ths
2007-01-24EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.ths
2007-01-24Reworking MIPS interrupt handling, by Aurelien Jarno.ths
2007-01-23Implementing dmfc/dmtc.ths
2007-01-22Fix PageMask handling, second part.ths
2006-12-23Check ELF binaries for machine type and endianness.ths
2006-12-21Scrap SIGN_EXTEND32.ths
2006-12-21Preliminiary MIPS64 support, disabled by default due to performance impact.ths
2006-12-06Add MIPS32R2 instructions, and generally straighten out the instructionths
2006-12-06Halt/reboot support for Linux, by Daniel Jacobowitz. This is a band-aidths
2006-12-06MIPS TLB performance improvements, by Daniel Jacobowitz.ths