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AgeCommit message (Expand)Author
2014-01-08target-arm: Use VFP_BINOP macro for min, max, minnum, maxnumPeter Maydell
2014-01-08target-arm: A64: Fix vector register access on bigendian hostsPeter Maydell
2014-01-08target-arm: A64: Add support for dumping AArch64 VFP register stateAlexander Graf
2014-01-08target-arm: A64: support for ld/st/cl exclusiveMichael Matz
2014-01-08target-arm: Widen exclusive-access support struct fields to 64 bitsPeter Maydell
2014-01-08target-arm: aarch64: add support for ld litAlexander Graf
2014-01-08target-arm: A64: add support for conditional compare insnsClaudio Fontana
2014-01-08target-arm: A64: add support for add/sub with carryClaudio Fontana
2014-01-07target-arm: Widen thread-local register state fields to 64 bitsPeter Maydell
2014-01-07target-arm: A64: Implement minimal set of EL0-visible sysregsPeter Maydell
2014-01-07target-arm: A64: Implement MRS/MSR/SYS/SYSLPeter Maydell
2014-01-07target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoderPeter Maydell
2014-01-06hw: Remove assert_no_error usagesPeter Crosthwaite
2014-01-04target-arm: Update generic cpreg code for AArch64Peter Maydell
2014-01-04target-arm: Pull "add one cpreg to hashtable" into its own functionPeter Maydell
2013-12-23target-arm: A64: implement FMOVPeter Maydell
2013-12-23target-arm: A64: Add decoder skeleton for FP instructionsPeter Maydell
2013-12-23target-arm: A64: implement SVC, BRKAlexander Graf
2013-12-23target-arm: A64: add support for 3 src data proc insnsAlexander Graf
2013-12-23target-arm: A64: add support for move wide instructionsAlex Bennée
2013-12-23target-arm: A64: add support for add, addi, sub, subiAlex Bennée
2013-12-23target-arm: A64: add support for ld/st with indexAlex Bennée
2013-12-23target-arm: A64: add support for ld/st with reg offsetAlex Bennée
2013-12-23target-arm: A64: add support for ld/st unsigned immAlex Bennée
2013-12-23target-arm: A64: add support for ld/st pairPeter Maydell
2013-12-17target-arm: A64: add support for logical (immediate) insnsAlexander Graf
2013-12-17target-arm: A64: add support for 1-src CLS insnClaudio Fontana
2013-12-17target-arm: A64: add support for bitfield insnsClaudio Fontana
2013-12-17target-arm: A64: add support for 1-src REV insnsClaudio Fontana
2013-12-17target-arm: A64: add support for 1-src RBIT insnAlexander Graf
2013-12-17target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana
2013-12-17target-arm: A64: add support for 2-src shift reg insnsAlexander Graf
2013-12-17target-arm: A64: add support for 2-src data processing and DIVAlexander Graf
2013-12-17target-arm: A64: add support for EXTRAlexander Graf
2013-12-17target-arm: A64: add support for ADR and ADRPAlexander Graf
2013-12-17target-arm: A64: add support for logical (shifted register)Alexander Graf
2013-12-17target-arm: A64: add support for conditional selectClaudio Fontana
2013-12-17target-arm: A64: add support for compare and branch immAlexander Graf
2013-12-17target-arm: A64: add support for 'test and branch' immAlexander Graf
2013-12-17target-arm: A64: add support for conditional branchesAlexander Graf
2013-12-17target-arm: A64: add support for BR, BLR and RET insnsAlexander Graf
2013-12-17target-arm: A64: add support for B and BL insnsAlexander Graf
2013-12-17target-arm: A64: expand decoding skeleton for system instructionsClaudio Fontana
2013-12-17target-arm: A64: provide skeleton for a64 insn decodingClaudio Fontana
2013-12-17target-arm: A64: add stubs for a64 specific helpersAlexander Graf
2013-12-17target-arm: Support fp registers in gdb stubPeter Maydell
2013-12-17target-arm: A64: provide functions for accessing FPCR and FPSRPeter Maydell
2013-12-17target-arm: A64: add set_pc cpu methodAlexander Graf
2013-12-17target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()Peter Maydell
2013-12-17target-arm: Add minimal KVM AArch64 supportMian M. Hamayun
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