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AgeCommit message (Expand)Author
2014-10-24target-arm: A32: Emulate the SMC instructionFabian Aggeler
2014-10-24target-arm: make arm_current_el() return EL3Fabian Aggeler
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows
2014-10-24target-arm: reject switching to monitor modeSergey Fedorov
2014-10-24target-arm: add arm_is_secure() functionFabian Aggeler
2014-10-24target-arm: increase arrays of registers R13 & R14Fabian Aggeler
2014-10-24target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell
2014-10-24target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"Peter Maydell
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring
2014-10-24target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell
2014-10-24target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell
2014-10-24target-arm: add missing PSCI constants needed for PSCI emulationArd Biesheuvel
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring
2014-10-24target-arm: add powered off cpu stateRob Herring
2014-10-06gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias
2014-09-29target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias
2014-09-29target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias
2014-09-29target-arm: A64: Correct updates to FAR and ESR on exceptionsEdgar E. Iglesias
2014-09-29target-arm: Don't take interrupts targeting lower ELsEdgar E. Iglesias
2014-09-29target-arm: Break out exception masking to a separate funcEdgar E. Iglesias
2014-09-29target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias
2014-09-29target-arm: Add SCR_EL3Edgar E. Iglesias
2014-09-29target-arm: Add HCR_EL2Edgar E. Iglesias
2014-09-29target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell
2014-09-29target-arm: Implement handling of breakpoint firingPeter Maydell
2014-09-29target-arm: Implement setting guest breakpointsPeter Maydell
2014-09-25target-arm: Use cpu_exec_interrupt qom hookRichard Henderson
2014-09-12target-arm: Make *IS TLB maintenance ops affect all CPUsPeter Maydell
2014-09-12target-arm: Push legacy wildcard TLB ops back into v6Peter Maydell
2014-09-12target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0Peter Maydell
2014-09-12target-arm: Remove comment about MDSCR_EL1 being dummy implementationPeter Maydell
2014-09-12target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32Peter Maydell
2014-09-12target-arm: Implement handling of fired watchpointsPeter Maydell
2014-09-12target-arm: Move extended_addresses_enabled() to internals.hPeter Maydell
2014-09-12target-arm: Implement setting of watchpointsPeter Maydell
2014-09-12target-arm: Fix broken indentation in arm_cpu_reest()Martin Galvan
2014-09-12target-arm: Fix resetting issues on ARMv7-M CPUsMartin Galvan
2014-08-29target-arm: Implement pmccfiltr_write functionAlistair Francis
2014-08-29target-arm: Remove old code and replace with new functionsAlistair Francis
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis
2014-08-29target-arm: Add arm_ccnt_enabled functionAlistair Francis
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis
2014-08-29arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis
2014-08-29target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register valuesPeter Maydell
2014-08-29target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell
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