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QEMU is a generic and open source machine & userspace emulator and virtualizer.
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target-arm
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translate-a64.c
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Author
2016-09-16
target-aarch64: Generate fences for aarch64
Pranith Kumar
2016-06-06
target-arm: A64: Create Instruction Syndromes for Data Aborts
Edgar E. Iglesias
2016-05-19
cpu: move exec-all.h inclusion out of cpu.h
Paolo Bonzini
2016-05-12
tcg: Allow goto_tb to any target PC in user mode
Sergey Fedorov
2016-05-12
target-arm/translate-a64.c: Unify some of the ldst_reg decoding
Edgar E. Iglesias
2016-05-12
target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9
Edgar E. Iglesias
2016-03-22
target-arm: dfilter support for in_asm
Alex Bennée
2016-03-04
target-arm: introduce tbflag for endianness
Peter Crosthwaite
2016-03-04
target-arm: a64: Add endianness support
Peter Crosthwaite
2016-03-04
target-arm: introduce disas flag for endianness
Paolo Bonzini
2016-03-04
target-arm: implement SCTLR.B, drop bswap_code
Paolo Bonzini
2016-02-11
target-arm: Add isread parameter to CPAccessFns
Peter Maydell
2016-02-09
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr
Richard Henderson
2016-02-03
log: do not unnecessarily include qom/cpu.h
Paolo Bonzini
2016-01-18
target-arm: Clean up includes
Peter Maydell
2015-11-24
target-arm/translate-a64.c: Correct unallocated checks for ldst_excl
Peter Maydell
2015-11-12
target-arm: Update PC before calling gen_helper_check_breakpoints()
Sergey Fedorov
2015-11-03
target-arm: Report S/NS status in the CPU debug logs
Peter Maydell
2015-11-03
target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32
Peter Maydell
2015-10-28
target-*: Advance pc after recognizing a breakpoint
Richard Henderson
2015-10-16
target-arm: Fix CPU breakpoint handling
Sergey Fedorov
2015-10-16
target-arm: Break the TB after ISB to execute self-modified code correctly
Sergey Sorokin
2015-10-07
tcg: Remove gen_intermediate_code_pc
Richard Henderson
2015-10-07
tcg: Add TCG_MAX_INSNS
Richard Henderson
2015-10-07
target-arm: Add condexec state to insn_start
Richard Henderson
2015-10-07
target-*: Introduce and use cpu_breakpoint_test
Richard Henderson
2015-10-07
target-*: Increment num_insns immediately after tcg_gen_insn_start
Richard Henderson
2015-10-07
target-*: Unconditionally emit tcg_gen_insn_start
Richard Henderson
2015-10-07
tcg: Rename debug_insn_start to insn_start
Richard Henderson
2015-09-14
target-arm: Use tcg_gen_extrh_i64_i32
Richard Henderson
2015-09-14
target-arm: Recognize ROR
Richard Henderson
2015-09-14
target-arm: Eliminate unnecessary zero-extend in disas_bitfield
Richard Henderson
2015-09-14
target-arm: Recognize UXTB, UXTH, LSR, LSL
Richard Henderson
2015-09-14
target-arm: Recognize SXTB, SXTH, SXTW, ASR
Richard Henderson
2015-09-14
target-arm: Implement fcsel with movcond
Richard Henderson
2015-09-14
target-arm: Implement ccmp branchless
Richard Henderson
2015-09-14
target-arm: Use setcond and movcond for csel
Richard Henderson
2015-09-14
target-arm: Share all common TCG temporaries
Richard Henderson
2015-09-08
target-arm: Fix default_exception_el() function for the case when EL3 is not ...
Sergey Sorokin
2015-09-07
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
Peter Maydell
2015-08-24
tcg: Remove tcg_gen_trunc_i64_i32
Richard Henderson
2015-07-06
target-arm: Split DISAS_YIELD from DISAS_WFE
Peter Maydell
2015-06-22
disas: Remove uses of CPU env
Peter Crosthwaite
2015-05-29
target-arm: Don't halt on WFI unless we don't have any work
Peter Maydell
2015-05-29
target-arm: Extend FP checks to use an EL
Greg Bellows
2015-05-29
target-arm: Make singlestate TB flags common between AArch32/64
Peter Maydell
2015-05-29
target-arm: Add exception target el infrastructure
Greg Bellows
2015-03-13
tcg: Change translator-side labels to a pointer
Richard Henderson
2015-02-13
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150212' into staging
Peter Maydell
2015-02-13
target-arm: A64: Avoid signed shifts in disas_ldst_pair()
Peter Maydell
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