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QEMU is a generic and open source machine & userspace emulator and virtualizer.
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translate-a64.c
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2015-02-13
target-arm: A64: Fix shifts into sign bit
Peter Maydell
2015-02-12
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
Richard Henderson
2015-02-12
tcg: Move emit of INDEX_op_end into gen_tb_end
Richard Henderson
2015-02-05
target-arm: Use correct mmu_idx for unprivileged loads and stores
Peter Maydell
2015-02-05
target-arm: Define correct mmu_idx values and pass them in TB flags
Peter Maydell
2015-02-05
target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT
Peter Maydell
2015-01-03
gen-icount: check cflags instead of use_icount global
Paolo Bonzini
2015-01-03
translate: check cflags instead of use_icount global
Paolo Bonzini
2014-11-02
target-arm: A64: remove redundant store
Alex Bennée
2014-10-24
target-arm: rename arm_current_pl to arm_current_el
Greg Bellows
2014-10-24
target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers
Peter Maydell
2014-09-29
target-arm: A64: Emulate the SMC insn
Edgar E. Iglesias
2014-09-29
target-arm: A64: Emulate the HVC insn
Edgar E. Iglesias
2014-08-19
target-arm: Implement ARMv8 single-step handling for A64 code
Peter Maydell
2014-08-19
target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb
Peter Maydell
2014-08-19
target-arm: Fix return address for A64 BRK instructions
Peter Maydell
2014-08-12
trace: [tcg] Include TCG-tracing header on all targets
Lluís Vilanova
2014-06-19
target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()
Peter Maydell
2014-06-19
target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()
Peter Maydell
2014-06-09
target-arm: A64: Implement two-register SHA instructions
Peter Maydell
2014-06-09
target-arm: A64: Implement 3-register SHA instructions
Peter Maydell
2014-06-09
target-arm: A64: Implement AES instructions
Peter Maydell
2014-06-09
target-arm: A64: Implement CRC instructions
Peter Maydell
2014-06-09
target-arm: A64: Use PMULL feature bit for PMULL
Peter Maydell
2014-06-05
target-arm: move arm_*_code to a separate file
Paolo Bonzini
2014-05-28
tcg: Invert the inclusion of helper.h
Richard Henderson
2014-05-27
target-arm: A64: Trap ERET from EL0 at translation time
Edgar E. Iglesias
2014-05-27
target-arm: Move get_mem_index to translate.h
Edgar E. Iglesias
2014-05-01
target-arm: A64: Handle blr lr
Edgar E. Iglesias
2014-05-01
target-arm: implement WFE/YIELD as a yield for AArch64
Rob Herring
2014-04-17
target-arm: A64: fix unallocated test of scalar SQXTUN
Alex Bennée
2014-04-17
target-arm: Implement AArch64 EL1 exception handling
Rob Herring
2014-04-17
target-arm: A64: Implement DC ZVA
Peter Maydell
2014-04-17
target-arm: A64: Add assertion that FP access was checked
Peter Maydell
2014-04-17
target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
Peter Maydell
2014-04-17
target-arm: Add support for generating exceptions with syndrome information
Peter Maydell
2014-04-17
target-arm: Provide correct syndrome information for cpreg access traps
Peter Maydell
2014-04-17
target-arm: Split out private-to-target functions into internals.h
Peter Maydell
2014-03-24
target-arm: Fix A64 Neon MLS
Peter Maydell
2014-03-18
target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)
Alex Bennée
2014-03-18
target-arm: A64: Add saturating int ops (SQNEG/SQABS)
Alex Bennée
2014-03-17
target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
Alex Bennée
2014-03-17
target-arm: A64: Implement FCVTXN
Peter Maydell
2014-03-17
target-arm: A64: Implement scalar saturating narrow ops
Alex Bennée
2014-03-17
target-arm: A64: Move handle_2misc_narrow function
Alex Bennée
2014-03-17
target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
Alex Bennée
2014-03-17
target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
Peter Maydell
2014-03-17
target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
Peter Maydell
2014-03-17
target-arm: A64: Implement FRINT*
Peter Maydell
2014-03-17
target-arm: A64: Implement SRI
Peter Maydell
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