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path: root/target-arm/helper.c
AgeCommit message (Expand)Author
2015-09-15target-arm: Use new revbit functionsRichard Henderson
2015-09-14target-arm: Add VMPIDR_EL2Edgar E. Iglesias
2015-09-14target-arm: Break out mpidr_read_val()Edgar E. Iglesias
2015-09-14target-arm: Add VPIDR_EL2Edgar E. Iglesias
2015-09-14target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias
2015-09-14target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias
2015-09-14target-arm: Add VTTBR_EL2Edgar E. Iglesias
2015-09-14target-arm: Add VTCR_EL2Edgar E. Iglesias
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt
2015-09-11maint: remove / fix many doubled wordsDaniel P. Berrange
2015-09-08target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias
2015-09-08target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias
2015-09-07target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin
2015-09-07arm: Remove hw_error() usages.Peter Crosthwaite
2015-09-07target-arm: Improve semihosting debug printsChristopher Covington
2015-08-25target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell
2015-08-25target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell
2015-08-25target-arm: Implement missing EL2 TLBI operationsPeter Maydell
2015-08-25target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell
2015-08-25target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell
2015-08-25target-arm: Implement AArch32 ATS1H* operationsPeter Maydell
2015-08-25target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell
2015-08-25target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell
2015-08-25target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell
2015-08-25target-arm: Implement missing ACTLR registersPeter Maydell
2015-08-25target-arm: Implement missing AFSR registersPeter Maydell
2015-08-25target-arm: Implement missing AMAIR registersPeter Maydell
2015-08-25target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell
2015-08-13target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell
2015-08-13target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell
2015-08-13target-arm: Add debug check for mismatched cpreg resetsPeter Maydell
2015-08-13target-arm: Add the Hypervisor timerEdgar E. Iglesias
2015-08-13target-arm: Pass timeridx as argument to various timer functionsEdgar E. Iglesias
2015-08-13target-arm: Rename and move gt_cnt_resetEdgar E. Iglesias
2015-08-13target-arm: Add CNTHCTL_EL2Edgar E. Iglesias
2015-08-13target-arm: Add CNTVOFF_EL2Edgar E. Iglesias
2015-07-15target-arm: Fix broken SCTLR_EL3 resetPeter Maydell
2015-07-06target-arm: fix write helper for TLBI ALLE1ISSergey Fedorov
2015-06-19semihosting: create SemihostingConfig structure and semihost.hLeon Alrae
2015-06-19target-arm: Implement PMSAv7 MPUPeter Crosthwaite
2015-06-19target-arm: Add registers for PMSAv7Peter Crosthwaite
2015-06-19target-arm/helper.c: define MPUIR registerPeter Crosthwaite
2015-06-19target-arm: Do not reset sysregs marked as ALIASSergey Fedorov
2015-06-15arm: helper: rename get_phys_addr_mpuPeter Crosthwaite
2015-06-15arm: Implement uniprocessor with MP configPeter Crosthwaite
2015-06-15arm: Refactor get_phys_addr FSR return mechanismPeter Crosthwaite
2015-06-15arm: helper: Factor out CP regs common to [pv]msaPeter Crosthwaite
2015-06-15arm: Don't add v7mp registers in MPU systemsPeter Crosthwaite
2015-06-15arm: Do not define TLBTR in PMSA systemsPeter Crosthwaite
2015-06-15target-arm: Use the kernel's idea of MPIDR if we're using KVMPavel Fedin
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