qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2020-02-27	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	Anup Patel
2020-02-10	riscv: virt: Use Goldfish RTC device	Anup Patel
2019-11-25	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	Zhuang, Siwei (Data61, Kensington NSW)
2019-10-28	riscv/virt: Add the PFlash CFI01 device	Alistair Francis
2019-10-28	riscv/virt: Manually define the machine	Alistair Francis
2019-10-28	riscv/sifive_u: Add the start-in-flash property	Alistair Francis
2019-10-28	riscv/sifive_u: Manually define the machine	Alistair Francis
2019-10-28	riscv/sifive_u: Add QSPI memory region	Alistair Francis
2019-10-28	riscv/sifive_u: Add L2-LIM cache memory	Alistair Francis
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng
2019-09-17	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	Bin Meng
2019-09-17	riscv: sifive_u: Fix broken GEM support	Bin Meng
2019-09-17	riscv: sifive_u: Instantiate OTP memory with a serial number	Bin Meng
2019-09-17	riscv: sifive: Implement a model for SiFive FU540 OTP	Bin Meng
2019-09-17	riscv: sifive_u: Update UART base addresses and IRQs	Bin Meng
2019-09-17	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	Bin Meng
2019-09-17	riscv: sifive_u: Add PRCI block to the SoC	Bin Meng
2019-09-17	riscv: sifive_u: Generate hfclk and rtcclk nodes	Bin Meng
2019-09-17	riscv: sifive: Implement PRCI model for FU540	Bin Meng
2019-09-17	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	Bin Meng
2019-09-17	riscv: sifive_u: Set the minimum number of cpus to 2	Bin Meng
2019-09-17	riscv: hart: Add a "hartid-base" property to RISC-V hart array	Bin Meng
2019-09-17	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	Bin Meng
2019-09-17	riscv: sifive_e: prci: Update the PRCI register block size	Bin Meng
2019-09-17	riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}	Bin Meng
2019-09-17	riscv: sifive_test: Add reset functionality	Bin Meng
2019-09-17	riscv: Add a helper routine for finding firmware	Bin Meng
2019-09-17	riscv: plic: Remove unused interrupt functions	Alistair Francis
2019-08-16	Clean up inclusion of sysemu/sysemu.h	Markus Armbruster
2019-08-16	Include hw/hw.h exactly where needed	Markus Armbruster
2019-08-16	include: Make headers more self-contained	Markus Armbruster
2019-07-18	hw/riscv: Load OpenSBI as the default firmware	Alistair Francis
2019-06-27	hw/riscv: Add support for loading a firmware	Alistair Francis
2019-06-27	hw/riscv: Split out the boot functions	Alistair Francis
2019-06-23	RISC-V: Fix a memory leak when realizing a sifive_e	Palmer Dabbelt
2019-06-23	sifive_prci: Read and write PRCI registers	Nathaniel Graff
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis
2019-05-24	SiFive RISC-V GPIO Device	Fabien Chouteau
2019-05-13	Clean up decorations and whitespace around header guards	Markus Armbruster
2019-04-04	riscv: plic: Fix incorrect irq calculation	Alistair Francis
2018-12-20	sifive_uart: Implement interrupt pending register	Nathaniel Graff
2018-12-20	sifive_u: Add clock DT node for GEM ethernet	Anup Patel
2018-12-20	hw/riscv/virt: Connect the gpex PCIe	Alistair Francis
2018-12-20	hw/riscv/virt: Increase the number of interrupts	Alistair Francis
2018-09-04	RISC-V: Use atomic_cmpxchg to update PLIC bitmaps	Michael Clark
2018-07-05	hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device	Alistair Francis
2018-07-05	hw/riscv/sifive_plic: Use gpios instead of irqs	Alistair Francis
2018-07-05	hw/riscv/sifive_e: Create a SiFive E SoC object	Alistair Francis
2018-07-05	hw/riscv/sifive_u: Create a SiFive U SoC object	Alistair Francis
2018-05-06	RISC-V: Make virt header comment title consistent	Michael Clark