summaryrefslogtreecommitdiff
path: root/hw/riscv
AgeCommit message (Expand)Author
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis
2020-10-22hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis
2020-10-22hw/riscv: Return the end address of the loaded firmwareAlistair Francis
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis
2020-09-25load_elf: Remove unused address variables from callersBALATON Zoltan
2020-09-22sifive_u: Register "start-in-flash" as class propertyEduardo Habkost
2020-09-22sifive_e: Register "revb" as class propertyEduardo Habkost
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost
2020-09-18sifive_e: Rename memmap enum constantsEduardo Habkost
2020-09-09hw/riscv: Sort the Kconfig options in alphabetical orderBin Meng
2020-09-09hw/riscv: Drop CONFIG_SIFIVEBin Meng
2020-09-09hw/riscv: Always build riscv_hart.cBin Meng
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_gpio model to hw/gpioBin Meng
2020-09-09hw/riscv: Move sifive_u_otp model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_u_prci model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng
2020-09-09hw/riscv: hart: Add a new 'resetvec' propertyBin Meng
2020-09-09riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor
2020-09-08configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini
2020-08-27opentitan: Rename memmap enum constantsEduardo Habkost
2020-08-25hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel
2020-08-25hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel
2020-08-25hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel
2020-08-21hw/riscv: spike: Change the default bios to use generic platform imageBin Meng
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng
2020-08-21hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng
2020-08-21meson: convert hw/arch*Marc-André Lureau
2020-08-21trace: switch position of headers to what Meson requiresPaolo Bonzini
2020-07-22hw/riscv: sifive_e: Correct debug block sizeBin Meng
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng
2020-07-13RISC-V: Support 64 bit start addressAtish Patra
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 18:58:06 +0000