qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2021-09-01	hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()	Peter Maydell
2021-09-01	hw/riscv: virt: Move flash node to root	Bin Meng
2021-09-01	hw/char: Add config for shakti uart	Vijai Kumar K
2021-08-26	arch_init.h: Don't include arch_init.h unnecessarily	Peter Maydell
2021-07-20	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	Philippe Mathieu-Daudé
2021-07-15	hw/riscv/boot: Check the error of fdt_pack()	Alistair Francis
2021-07-15	hw/riscv: opentitan: Add the flash alias	Alistair Francis
2021-07-15	hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri	Alistair Francis
2021-07-15	hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned	Bin Meng
2021-07-15	hw/riscv: sifive_u: Correct the CLINT timebase frequency	Bin Meng
2021-06-24	hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer	Alistair Francis
2021-06-08	hw/riscv: microchip_pfsoc: Support direct kernel boot	Bin Meng
2021-06-08	hw/riscv: Use macros for BIOS image names	Bin Meng
2021-06-08	hw/riscv: Support the official PLIC DT bindings	Bin Meng
2021-06-08	hw/riscv: Support the official CLINT DT bindings	Bin Meng
2021-06-08	hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper	Bin Meng
2021-06-08	hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper	Bin Meng
2021-05-11	hw/riscv: Fix OT IBEX reset vector	Alexander Wagner
2021-05-11	hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine	Alistair Francis
2021-05-11	hw/opentitan: Update the interrupt layout	Alistair Francis
2021-05-11	hw/riscv: Connect Shakti UART to Shakti platform	Vijai Kumar K
2021-05-11	riscv: Add initial support for Shakti C machine	Vijai Kumar K
2021-05-11	hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]	Bin Meng
2021-05-02	Do not include exec/address-spaces.h if it's not really necessary	Thomas Huth
2021-05-02	hw: Do not include qemu/log.h if it is not necessary	Thomas Huth
2021-05-02	hw: Do not include hw/irq.h if it is not necessary	Thomas Huth
2021-03-22	hw/riscv: microchip_pfsoc: Map EMMC/SD mux register	Bin Meng
2021-03-22	hw/riscv: allow ramfb on virt	Asherah Connor
2021-03-22	hw/riscv: Add fw_cfg support to virt	Asherah Connor
2021-03-11	Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-docs-xen-upda...	Peter Maydell
2021-03-10	hw/riscv: migrate fdt field to generic MachineState	Alex Bennée
2021-03-09	qtest: delete superfluous inclusions of qtest.h	Chen Qun
2021-03-04	hw/riscv: virt: Map high mmio for PCIe	Bin Meng
2021-03-04	hw/riscv: virt: Limit RAM size in a 32-bit system	Bin Meng
2021-03-04	hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()	Bin Meng
2021-03-04	hw/riscv: Drop 'struct MemmapEntry'	Bin Meng
2021-03-04	hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card	Bin Meng
2021-03-04	hw/riscv: sifive_u: Add QSPI0 controller and connect a flash	Bin Meng
2021-01-16	riscv: Pass RISCVHartArrayState by pointer	Alistair Francis
2021-01-16	hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type	Bin Meng
2021-01-16	RISC-V: Place DTB at 3GB boundary instead of 4GB	Atish Patra
2020-12-17	riscv/opentitan: Update the OpenTitan memory layout	Alistair Francis
2020-12-17	hw/riscv: Use the CPU to determine if 32-bit	Alistair Francis
2020-12-17	hw/riscv: sifive_u: Remove compile time XLEN checks	Alistair Francis
2020-12-17	hw/riscv: spike: Remove compile time XLEN checks	Alistair Francis
2020-12-17	hw/riscv: virt: Remove compile time XLEN checks	Alistair Francis
2020-12-17	hw/riscv: boot: Remove compile time XLEN checks	Alistair Francis
2020-12-17	riscv: virt: Remove target macro conditionals	Alistair Francis
2020-12-17	riscv: spike: Remove target macro conditionals	Alistair Francis
2020-12-17	hw/riscv: Expand the is 32-bit check to support more CPUs	Alistair Francis