qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2019-05-24	riscv: spike: Add a generic spike machine	Alistair Francis
2019-05-24	riscv: virt: Allow specifying a CPU via commandline	Alistair Francis
2019-05-24	target/riscv: Remove unused include of riscv_htif.h for virt board riscv	Jonathan Behrens
2019-05-24	SiFive RISC-V GPIO Device	Fabien Chouteau
2019-04-04	riscv: plic: Log guest errors	Alistair Francis
2019-04-04	riscv: plic: Fix incorrect irq calculation	Alistair Francis
2019-03-28	Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging	Peter Maydell
2019-03-19	riscv: sifive_u: Correct UART0's IRQ in the device tree	Bin Meng
2019-03-19	riscv: sifive_uart: Generate TX interrupt	Bin Meng
2019-03-19	riscv: sifive_u: Allow up to 4 CPUs to be created	Alistair Francis
2019-03-19	RISC-V: Allow interrupt controllers to claim interrupts	Michael Clark
2019-03-19	RISC-V: Replace __builtin_popcount with ctpop8 in PLIC	Michael Clark
2019-03-18	kconfig: add CONFIG_MSI_NONBROKEN	Paolo Bonzini
2019-03-18	riscv: plic: Set msi_nonbroken as true	Alistair Francis
2019-03-11	riscv/Kconfig: enable PCI_DEVICES	David Abdurachmanov
2019-03-07	riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives	Paolo Bonzini
2019-03-07	kconfig: introduce kconfig files	Paolo Bonzini
2019-02-11	riscv: Ensure the kernel start address is correctly cast	Alistair Francis
2019-02-05	hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards	Yang Zhong
2019-02-05	elf: Add optional function ptr to load_elf() to parse ELF notes	Liam Merwick
2018-12-20	sifive_uart: Implement interrupt pending register	Nathaniel Graff
2018-12-20	RISC-V: Enable second UART on sifive_e and sifive_u	Michael Clark
2018-12-20	RISC-V: Fix PLIC pending bitfield reads	Michael Clark
2018-12-20	RISC-V: Fix CLINT timecmp low 32-bit writes	Michael Clark
2018-12-20	sifive_u: Set 'clock-frequency' DT property for SiFive UART	Anup Patel
2018-12-20	sifive_u: Add clock DT node for GEM ethernet	Anup Patel
2018-12-20	hw/riscv/virt: Connect the gpex PCIe	Alistair Francis
2018-12-20	hw/riscv/virt: Adjust memory layout spacing	Alistair Francis
2018-11-13	hw/riscv/virt: Free the test device tree node name	Alistair Francis
2018-11-08	riscv: spike: Fix memory leak in the board init	Alistair Francis
2018-10-17	RISC-V: Don't add NULL bootargs to device-tree	Michael Clark
2018-10-17	RISC-V: Add missing free for plic_hart_config	Michael Clark
2018-10-17	RISC-V: Allow setting and clearing multiple irqs	Michael Clark
2018-09-25	Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' into...	Peter Maydell
2018-09-24	Drop "qemu:" prefix from error_report() arguments	Mao Zhongyi
2018-09-05	hw/riscv/spike: Set the soc device tree node as a simple-bus	Alistair Francis
2018-09-05	hw/riscv/virtio: Set the soc device tree node as a simple-bus	Alistair Francis
2018-09-04	RISC-V: Use atomic_cmpxchg to update PLIC bitmaps	Michael Clark
2018-07-19	spike: Fix crash when introspecting the device	Alistair Francis
2018-07-19	riscv_hart: Fix crash when introspecting the device	Alistair Francis
2018-07-19	virt: Fix crash when introspecting the device	Alistair Francis
2018-07-19	sifive_u: Fix crash when introspecting the device	Alistair Francis
2018-07-19	sifive_e: Fix crash when introspecting the device	Alistair Francis
2018-07-05	hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device	Alistair Francis
2018-07-05	hw/riscv/sifive_u: Move the uart device tree node under /soc/	Alistair Francis
2018-07-05	hw/riscv/sifive_u: Set the interrupt controller number of interrupts	Alistair Francis
2018-07-05	hw/riscv/sifive_u: Set the soc device tree node as a simple-bus	Alistair Francis
2018-07-05	hw/riscv/sifive_plic: Use gpios instead of irqs	Alistair Francis
2018-07-05	hw/riscv/sifive_e: Create a SiFive E SoC object	Alistair Francis
2018-07-05	hw/riscv/sifive_u: Create a SiFive U SoC object	Alistair Francis