qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2020-03-16	riscv: sifive_u: Update BIOS_FILENAME for 32-bit	Bin Meng
2020-03-03	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...	Peter Maydell
2020-02-28	hw: Make MachineClass::is_default a boolean type	Philippe Mathieu-Daudé
2020-02-27	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	Anup Patel
2020-02-27	riscv: virt: Allow PCI address 0	Bin Meng
2020-02-10	riscv: virt: Use Goldfish RTC device	Anup Patel
2020-02-10	riscv/virt: Add syscon reboot and poweroff DT nodes	Anup Patel
2020-01-29	hw/core/loader: Let load_elf() populate a field with CPU-specific flags	Aleksandar Markovic
2020-01-27	Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging	Peter Maydell
2020-01-24	qdev: set properties with device_class_set_props()	Marc-André Lureau
2020-01-16	riscv/sifive_u: fix a memory leak in soc_realize()	Pan Nengyuan
2020-01-08	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	Philippe Mathieu-Daudé
2019-11-25	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	Zhuang, Siwei (Data61, Kensington NSW)
2019-11-25	RISC-V: virt: This is a "sifive,test1" test finisher	Palmer Dabbelt
2019-11-14	riscv/virt: Increase flash size	Alistair Francis
2019-10-28	riscv/boot: Fix possible memory leak	Alistair Francis
2019-10-28	riscv/virt: Jump to pflash if specified	Alistair Francis
2019-10-28	riscv/virt: Add the PFlash CFI01 device	Alistair Francis
2019-10-28	riscv/virt: Manually define the machine	Alistair Francis
2019-10-28	riscv/sifive_u: Add the start-in-flash property	Alistair Francis
2019-10-28	riscv/sifive_u: Manually define the machine	Alistair Francis
2019-10-28	riscv/sifive_u: Add QSPI memory region	Alistair Francis
2019-10-28	riscv/sifive_u: Add L2-LIM cache memory	Alistair Francis
2019-10-28	riscv: sifive_u: Add ethernet0 to the aliases node	Bin Meng
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng
2019-09-17	riscv: sifive_u: Update model and compatible strings in device tree	Bin Meng
2019-09-17	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	Bin Meng
2019-09-17	riscv: sifive_u: Fix broken GEM support	Bin Meng
2019-09-17	riscv: sifive_u: Instantiate OTP memory with a serial number	Bin Meng
2019-09-17	riscv: sifive: Implement a model for SiFive FU540 OTP	Bin Meng
2019-09-17	riscv: sifive_u: Change UART node name in device tree	Bin Meng
2019-09-17	riscv: sifive_u: Update UART base addresses and IRQs	Bin Meng
2019-09-17	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	Bin Meng
2019-09-17	riscv: sifive_u: Add PRCI block to the SoC	Bin Meng
2019-09-17	riscv: sifive_u: Generate hfclk and rtcclk nodes	Bin Meng
2019-09-17	riscv: sifive: Implement PRCI model for FU540	Bin Meng
2019-09-17	riscv: sifive_u: Update PLIC hart topology configuration string	Bin Meng
2019-09-17	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	Bin Meng
2019-09-17	riscv: sifive_u: Set the minimum number of cpus to 2	Bin Meng
2019-09-17	riscv: hart: Add a "hartid-base" property to RISC-V hart array	Bin Meng
2019-09-17	riscv: hart: Extract hart realize to a separate routine	Bin Meng
2019-09-17	riscv: sifive_e: Drop sifive_mmio_emulate()	Bin Meng
2019-09-17	riscv: sifive_e: prci: Update the PRCI register block size	Bin Meng
2019-09-17	riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming	Bin Meng
2019-09-17	riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}	Bin Meng
2019-09-17	riscv: sifive_u: Remove the unnecessary include of prci header	Bin Meng
2019-09-17	riscv: hw: Remove the unnecessary include of target/riscv/cpu.h	Bin Meng
2019-09-17	riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead	Bin Meng
2019-09-17	riscv: hw: Change create_fdt() to return void	Bin Meng
2019-09-17	riscv: hw: Remove not needed PLIC properties in device tree	Bin Meng