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path: root/hw/riscv/sifive_test.c
AgeCommit message (Expand)Author
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng
2020-09-09riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor
2020-06-15sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster
2020-06-15qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster
2019-09-17riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng
2019-09-17riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng
2019-09-17riscv: hw: Remove duplicated "hw/hw.h" inclusionBin Meng
2019-09-17riscv: sifive_test: Add reset functionalityBin Meng
2019-08-16Include hw/qdev-properties.h lessMarkus Armbruster
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster
2019-06-12Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster
2018-03-07SiFive RISC-V Test FinisherMichael Clark