Age | Commit message (Expand) | Author |
---|---|---|
2020-09-09 | hw/riscv: Move sifive_test model to hw/misc | Bin Meng |
2020-09-09 | riscv: sifive_test: Allow 16-bit writes to memory region | Nathan Chancellor |
2020-06-15 | sysbus: Convert to sysbus_realize() etc. with Coccinelle | Markus Armbruster |
2020-06-15 | qdev: Convert uses of qdev_create() with Coccinelle | Markus Armbruster |
2019-09-17 | riscv: hw: Remove the unnecessary include of target/riscv/cpu.h | Bin Meng |
2019-09-17 | riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead | Bin Meng |
2019-09-17 | riscv: hw: Remove duplicated "hw/hw.h" inclusion | Bin Meng |
2019-09-17 | riscv: sifive_test: Add reset functionality | Bin Meng |
2019-08-16 | Include hw/qdev-properties.h less | Markus Armbruster |
2019-08-16 | Include hw/hw.h exactly where needed | Markus Armbruster |
2019-06-12 | Include qemu/module.h where needed, drop it from qemu-common.h | Markus Armbruster |
2018-03-07 | SiFive RISC-V Test Finisher | Michael Clark |