qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2020-03-17	hw/riscv: Let devices own the MemoryRegion they create	Philippe Mathieu-Daudé
2020-03-17	hw/riscv: Use memory_region_init_rom() with read-only regions	Philippe Mathieu-Daudé
2020-02-27	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	Anup Patel
2019-11-25	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	Zhuang, Siwei (Data61, Kensington NSW)
2019-09-17	riscv: sifive_e: Drop sifive_mmio_emulate()	Bin Meng
2019-09-17	riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}	Bin Meng
2019-08-16	Include sysemu/sysemu.h a lot less	Markus Armbruster
2019-08-16	Include hw/hw.h exactly where needed	Markus Armbruster
2019-07-05	hw/riscv: Replace global smp variables with machine smp properties	Like Xu
2019-06-27	hw/riscv: Split out the boot functions	Alistair Francis
2019-06-23	RISC-V: Fix a memory leak when realizing a sifive_e	Palmer Dabbelt
2019-05-24	SiFive RISC-V GPIO Device	Fabien Chouteau
2019-02-11	riscv: Ensure the kernel start address is correctly cast	Alistair Francis
2019-02-05	elf: Add optional function ptr to load_elf() to parse ELF notes	Liam Merwick
2018-12-20	RISC-V: Enable second UART on sifive_e and sifive_u	Michael Clark
2018-09-24	Drop "qemu:" prefix from error_report() arguments	Mao Zhongyi
2018-07-19	sifive_e: Fix crash when introspecting the device	Alistair Francis
2018-07-05	hw/riscv/sifive_plic: Use gpios instead of irqs	Alistair Francis
2018-07-05	hw/riscv/sifive_e: Create a SiFive E SoC object	Alistair Francis
2018-05-06	RISC-V: Mark ROM read-only after copying in code	Michael Clark
2018-05-06	RISC-V: Remove EM_RISCV ELF_MACHINE indirection	Michael Clark
2018-05-06	RISC-V: Remove unused class definitions	Michael Clark
2018-05-06	RISC-V: Remove identity_translate from load_elf	Michael Clark
2018-04-26	Change references to serial_hds[] to serial_hd()	Peter Maydell
2018-03-07	SiFive Freedom E Series RISC-V Machine	Michael Clark