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2018-12-13musicpal: Convert sysbus init function to realize functionMao Zhongyi
Use DeviceClass rather than SysBusDeviceClass in mv88w8618_wlan_class_init(). Cc: jan.kiszka@web.de Cc: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20181130093852.20739-2-maozhongyi@cmss.chinamobile.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13Allow AArch64 processors to boot from a kernel placed over 4GBRicardo Perez Blanco
Architecturally, it's possible for an AArch64 machine to have all of its RAM over the 4GB mark, but our kernel/initrd loading code in boot.c assumes that the upper half of the addresses to load these images to is always zero. Write the whole 64 bit address into the bootloader code fragment, not just the low half. Note that, currently, none of the existing QEMU machines have their main memory over 4GBs, so this was not a user-visible bug. Signed-off-by: Ricardo Perez Blanco <ricardo.perez_blanco@nokia.com> [PMM: revised commit message and tweaked some long lines] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link()Li Qiang
The third argument of object_property_set_link() is the name of property, not related with the QOM type name, using the constant string instead. Signed-off-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 1542880825-2604-1-git-send-email-liq3ea@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-11virt: Eliminate separate instance_init functionsEduardo Habkost
All instance_init functions for all virt machine-types run exactly the same code, so we don't need separate functions. We only need to set instance_init for TYPE_VIRT_MACHINE. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20181205205827.19387-2-ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-12-11q35/440fx/arm/spapr: Add QEMU 4.0 machine typeAlex Williamson
Including all machine types that might have a pcie-root-port. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Message-Id: <154394083644.28192.8501647946108201466.stgit@gimli.home> Reviewed-by: Eric Auger <eric.auger@redhat.com> [ehabkost: fixed accidental recursion at spapr_machine_3_1_class_options()] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-11-28hw/arm/aspeed: Fix build issue with clang 3.4Thomas Huth
When using clang 3.4.2, compilation of QEMU fails like this: CC aarch64-softmmu/hw/arm/aspeed.o hw/arm/aspeed.c:36:3: error: redefinition of typedef 'AspeedBoardState' is a C11 feature [-Werror,-Wtypedef-redefinition] } AspeedBoardState; ^ include/hw/arm/aspeed.h:14:33: note: previous definition is here typedef struct AspeedBoardState AspeedBoardState; ^ 1 error generated. make[1]: *** [hw/arm/aspeed.o] Error 1 make: *** [subdir-aarch64-softmmu] Error 2 Remove the duplicated typedef to fix this issue. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 1543397736-8198-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-27hw/virt/arm: Add support for Cortex-A72 in virtZhiPeng Lu
Signed-off-by: ZhiPeng Lu <luzhipeng@uniudc.com> Message-id: 1543316565-1101590-1-git-send-email-luzhipeng@uniudc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-13hw/arm/sysbus-fdt: Only call match_fn callback if the type matchesEric Auger
Commit af7d64ede0b9 (hw/arm/sysbus-fdt: Allow device matching with DT compatible value) introduced a match_fn callback which gets called for each registered combo to check whether a sysbus device can be dynamically instantiated. However the callback gets called even if the device type does not match the binding combo typename field. This causes an assert when passing "-device ramfb" to the qemu command line as vfio_platform_match() gets called on a non vfio-platform device. To fix this regression, let's change the add_fdt_node() logic so that we first check the type and if the match_fn callback is defined, then we also call it. Binding combos only requesting a type check do not define the match_fn callback. Fixes: af7d64ede0b9 (hw/arm/sysbus-fdt: Allow device matching with DT compatible value) Signed-off-by: Eric Auger <eric.auger@redhat.com> Reported-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Message-id: 20181106184212.29377-1-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-06hw/arm/exynos4210: Zero memory allocated for Exynos4210StatePeter Maydell
In exynos4210_init() we allocate memory for an Exynos4210State struct. Generally devices can assume that the memory allocated for their state struct is zero-initialized; we broke that assumption here by using g_new(). Use g_new0() instead. (In particular, some code assumes that the various irq arrays in the Exynos4210Irq sub-struct are zero-initialized.) In the longer term, this code should be QOMified, and then the struct memory will be allocated elsewhere and by functions which always zero-initalize it; but for 3.1 this is a simple fix. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20181105151132.13884-1-peter.maydell@linaro.org
2018-11-02hw/arm: versal: Add a virtual Xilinx Versal boardEdgar E. Iglesias
Add a virtual Xilinx Versal board. This board is based on the Xilinx Versal SoC. The exact details of what peripherals are attached to this board will remain in control of QEMU. QEMU will generate an FDT on the fly for Linux and other software to auto-discover peripherals. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181102131913.1535-3-edgar.iglesias@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-02hw/arm: versal: Add a model of Xilinx Versal SoCEdgar E. Iglesias
Add a model of Xilinx Versal SoC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-02hw/arm/xilinx_zynq: Use the ARRAY_SIZE macroPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-02strongarm: mask off high[31:28] bits from dir and state registersPrasad J Pandit
The high[31:28] bits of 'direction' and 'state' registers of SA-1100/SA-1110 device are reserved. Setting them may lead to OOB 's->handler[]' array access issue. Mask off [31:28] bits to avoid it. Reported-by: Moguofang <moguofang@huawei.com> Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Message-id: 20181030114635.31232-1-ppandit@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-02hw/arm/nrf51_soc: Connect UART to nRF51 SoCJulia Suvorova
Wire up nRF51 UART in the corresponding SoC. Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-02hw/arm/virt: Set VIRT_COMPAT_3_0 compatEric Auger
We are missing the VIRT_COMPAT_3_0 definition and setting. Let's add them. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20181024085602.16611-1-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-29audio: use TYPE_MV88W8618_AUDIO instead of hardcoded stringMao Zhongyi
Cc: Jan Kiszka <jan.kiszka@web.de> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20181022074050.19638-4-maozhongyi@cmss.chinamobile.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-10-29audio: use object link instead of qdev property to pass wm8750 referenceMao Zhongyi
According to qdev-properties.h, properties of pointer type should be avoided, it seems a link type property is a good substitution. Cc: Jan Kiszka <jan.kiszka@web.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20181022074050.19638-3-maozhongyi@cmss.chinamobile.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-10-29audio: use TYPE_WM8750 instead of a hardcoded stringMao Zhongyi
Cc: Jan Kiszka <jan.kiszka@web.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20181022074050.19638-2-maozhongyi@cmss.chinamobile.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-10-24hw/arm/boot: Increase compliance with kernel arm64 boot protocolStewart Hildebrand
"The Image must be placed text_offset bytes from a 2MB aligned base address anywhere in usable system RAM and called there." For the virt board, we write our startup bootloader at the very bottom of RAM, so that bit can't be used for the image. To avoid overlap in case the image requests to be loaded at an offset smaller than our bootloader, we increment the load offset to the next 2MB. This fixes a boot failure for Xen AArch64. Signed-off-by: Stewart Hildebrand <stewart.hildebrand@dornerworks.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Message-id: b8a89518794b4436af0c151ed10de4fa@dornerworks.com [PMM: Rephrased a comment a bit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-16hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UARTJerome Forissier
Bindings for /secure-chosen and /secure-chosen/stdout-path have been proposed 1.5 years ago [1] and implemented in OP-TEE at the same time [2]. They've now been officially agreed on, so we can implement them in QEMU. This patch creates the property when the machine is secure. [1] https://patchwork.kernel.org/patch/9602401/ [2] https://github.com/OP-TEE/optee_os/commit/4dc31c52544a Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Message-id: 20181005080729.6480-1-jerome.forissier@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: commit message tweak] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-15hw/arm/virt: Allow dynamic vfio-platform devices againGeert Uytterhoeven
Allow the instantation of generic dynamic vfio-platform devices again, without the need to create a new device-specific vfio type. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-10-15hw/arm/sysbus-fdt: Allow device matching with DT compatible valueEric Auger
Up to now we have relied on the device type to identify a device tree node creation function. Since we would like the vfio-platform device to be instantiable with different compatible strings we introduce the capability to specialize the node creation depending on actual compatible value. NodeCreationPair is renamed into BindingEntry. The struct is enhanced with compat and match_fn() fields. We introduce a new matching function adapted to the vfio-platform generic device. Soon, the AMD XGBE can be instantiated with either manner, i.e.: -device vfio-amd-xgbe,host=e0900000.xgmac or using the new option line: -device vfio-platform,host=e0900000.xgmac Signed-off-by: Eric Auger <eric.auger@redhat.com> [geert: Match using compatible values in sysfs instead of user-supplied manufacturer/model options, reword] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-10-08virt: Suppress external aborts on virt-2.10 and earlierPeter Maydell
In commit c79c0a314c43b78 we enabled emulation of external aborts when the guest attempts to access a physical address with no mapped device. In commit 4672cbd7bed88dc6 we suppress this for most legacy boards to prevent breakage of previously working guests, but we didn't suppress it in the 'virt' board, with the rationale "we know that guests won't try to prod devices that we don't describe in the device tree or ACPI tables". This is mostly true, but we've had a report of a Linux guest image that this did break. The problem seems to be that the guest is (incorrectly) configured with a DEBUG_UART_PHYS value that tells it there is a uart at 0x10009000 (which is true for vexpress but not for virt), so in early bootup the kernel probes this bogus address. This is a misconfigured guest, so we don't need to worry about it too much, but we can arrange that guests that ran on QEMU v2.10 (before c79c0a314c43b78) will still run on the "virt-2.10" board model, by suppressing external aborts only for that version and earlier. This seems a reasonable compromise: "virt-2.10" is supposed to behave the same way that "virt" did in the 2.10 release, and making it do that provides a usable workaround for guests with bugs like this. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180925144127.31965-1-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2018-09-25hw/arm/aspeed: Add an Aspeed machine classCédric Le Goater
The code looks better, it removes duplicated lines and it will ease the introduction of common properties for the Aspeed machines. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180921161939.822-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/aspeed: change the FMC flash model of the AST2500 evbCédric Le Goater
The AST2500 evb is shipped with a W25Q256 which has a non volatile bit to make the chip operate in 4 Byte address mode at power up. This should be an interesting feature to model as it will exercise a bit more the SMC controllers and MMIO execution at boot time. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180921161939.822-3-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/smmuv3: fix eventq recording and IRQ triggerringEric Auger
The event queue management is broken today. Event records are not properly written as EVT_SET_* macro was not updating the actual event record. Also the event queue interrupt is not correctly triggered. Fixes: bb981004eaf4 ("hw/arm/smmuv3: Event queue recording helper") Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180921070138.10114-3-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/smmu-common: Fix the name of the iommu memory regionsEric Auger
At the point smmu_find_add_as() gets called, the bus number might not be computed. Let's change the name of IOMMU memory region and just use the devfn and an incrementing index. The name only is used for debug. Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180921070138.10114-2-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: changed 'uint' to 'unsigned int'] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25arm: Add BBC micro:bit machineJoel Stanley
This adds the base for a machine model of the BBC micro:bit: https://en.wikipedia.org/wiki/Micro_Bit This is a system with a nRF51 SoC containing the main processor, with various peripherals on board. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-4-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25arm: Add Nordic Semiconductor nRF51 SoCJoel Stanley
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-3-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: wrapped a few long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodesShannon Zhao
Like commit 16b4226(hw/acpi-build: Add a check for memory-less NUMA node ), it also needs to check memory length for NUMA nodes on ARM. Signed-off-by: Shannon Zhao <shannon.zhaosl@gmail.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20180911112643.19296-1-shenglong.zsl@alibaba-inc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/exynos4210: fix Exynos4210 UART supportBartlomiej Zolnierkiewicz
commit 97274d0c05d4 ("hw/char/exynos4210_uart.c: Remove unneeded handling of NULL chardev") broke Exynos4210 support as it removed NULL 'Chardev *chr' handling from exynos4210_uart_create() and currently exynos4210_init() always passes NULL as 'Chardev *chr' argument to exynos4210_uart_create() calls. Fix it by adding missing serial_hd() calls to exynos4210_init(). Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 9310418.Wg32kryeWE@amdc3058 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25scsi: move lsi53c8xx_create() callers to lsi53c8xx_handle_legacy_cmdline()Mark Cave-Ayland
As part of commits a64aa5785d "hw: Deprecate -drive if=scsi with non-onboard HBAs" and b891538e81 "hw/ppc/prep: Fix implicit creation of "-drive if=scsi" devices" the lsi53c895a_create() and lsi53c810_create() functions were added to wrap pci_create_simple() and scsi_bus_legacy_handle_cmdline(). Unfortunately this prevents us from changing qdev properties on the device and/or changing the PCI configuration. By switching over to using the new lsi53c8xx_handle_legacy_cmdline() function then the caller can now configure and realize the LSI SCSI device exactly as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> [arm parts] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-08-24hw/arm/mps2: Fix ID register errors on AN511 and AN385Peter Maydell
Fix MPS2 SCC config register values for the mps2-an511 and mps2-an385 boards: * the SCC_AID bits [23:20] specify the FPGA build target board revision, and the SCC_CFG4 register specifies the actual board revision, so these should have matching values. Claim to be board revision C, consistently -- we had the revision in the wrong part of SCC_AID. * SCC_ID bits [15:4] should be the board number in hex, not decimal Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180823175225.22612-1-peter.maydell@linaro.org
2018-08-24hw/arm/mps2-tz: Fix MPS2 SCC config register valuesPeter Maydell
Some of the config register values we were setting for the MPS2 SCC weren't correct: * the SCC_AID bits [23:20] specify the FPGA build target board revision, and the SCC_CFG4 register specifies the actual board revision, so these should have matching values. Claim to be board revision C, consistently -- we had the revision in the wrong part of SCC_AID. * SCC_ID bits [15:4] should be 0x505, not decimal 505 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-23-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24hw/arm/mps2-tz: Instantiate SPI controllersPeter Maydell
The SPI controllers in the MPS2 AN505 board are PL022s. We have a model of the PL022, so create these devices. We don't currently model the LCD controller that sits behind one of the PL022s; the others are intended to control devices that sit on the FPGA's general purpose SPI connector or "shield" expansion connectors. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-22-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24hw/arm/mps2-tz: Create PL081s and MSCsPeter Maydell
The AN505 FPGA image includes four PL081 DMA controllers, each of which is gated by a Master Security Controller that allows the guest to prevent a non-secure DMA controller from accessing memory that is used by secure guest code. Create and wire up these devices. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180820141116.9118-15-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24hw/arm/iotkit: Wire up the lines for MSCsPeter Maydell
The IoTKit doesn't have any MSCs itself but it does need some wiring to connect the external signals from MSCs in the outer board model up to the registers and the NVIC IRQ line. We also need to expose a MemoryRegion corresponding to the AHB bus, so that MSCs in the outer board model can use that as their downstream port. (In the FPGA this is the "AHB Slave Expansion" ports shown in the block diagram in the AN505 documentation.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180820141116.9118-14-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24hw/misc/iotkit: Wire up the sysctl and sysinfo register blocksPeter Maydell
Wire up the system control element's register banks (sysctl and sysinfo). This is the last of the previously completely unimplemented components in the IoTKit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-11-peter.maydell@linaro.org
2018-08-24hw/arm/iotkit: Wire up the S32KTIMERPeter Maydell
The IoTKit has a CMSDK timer device that runs on the S32KCLK. Create this and wire it up. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-8-peter.maydell@linaro.org
2018-08-24hw/arm/iotkit: Wire up the watchdogsPeter Maydell
The IoTKit includes three different instances of the CMSDK APB watchdog; create and wire them up. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-7-peter.maydell@linaro.org
2018-08-24hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511Peter Maydell
The MPS2 FPGA images for the Cortex-M3 (mps2-an385 and mps2-511) both include a CMSDK dual-timer module. Wire this up. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-6-peter.maydell@linaro.org
2018-08-24hw/arm/iotkit: Wire up the dualtimerPeter Maydell
Now we have a model of the CMSDK dual timer, we can wire it up in the IoTKit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-5-peter.maydell@linaro.org
2018-08-24hw/arm/boot: AArch32 kernels should be started in Hyp mode if availablePeter Maydell
The kernel booting specification for an AArch32 kernel requires that it is booted in Hyp mode if available; otherwise the kernel can't enable KVM. We were incorrectly leaving the kernel in SVC mode. If we're booting an AArch32 kernel in the Nonsecure state and Hyp mode is available, start in it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180820153020.21478-7-peter.maydell@linaro.org
2018-08-24hw/arm/vexpress: Add "virtualization" property controlling presence of EL2Peter Maydell
Add a "virtualization" property to the vexpress-a15 board, controlling presence of EL2. As with EL3, we default to enabling it, but the user can disable it if they have an older guest which can't cope with it being present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180821132811.17675-10-peter.maydell@linaro.org
2018-08-24hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3Peter Maydell
Don't request that the arm_load_kernel() code should boot in secure state if the CPU doesn't have a secure state. Currently this doesn't make a difference because the boot.c code only examines the secure_boot flag in code guarded by an ARM_FEATURE_EL3 check, but upcoming changes for supporting booting into Hyp mode will change that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180821132811.17675-9-peter.maydell@linaro.org
2018-08-24hw/arm/fsl-imx6ul: Connect VIRQ and VFIQPeter Maydell
Connect the VIRQ and VFIQ lines from the GIC to the CPU; these exist always for both CPU and GIC whether the virtualization extensions are enabled or not, so we can just unconditionally connect them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180821132811.17675-7-peter.maydell@linaro.org
2018-08-24hw/arm/fsl-imx6ul: Connect VIRQ and VFIQPeter Maydell
Connect the VIRQ and VFIQ lines from the GIC to the CPU; these exist always for both CPU and GIC whether the virtualization extensions are enabled or not, so we can just unconditionally connect them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180821132811.17675-6-peter.maydell@linaro.org
2018-08-24hw/arm/highbank: Connect VIRQ and VFIQPeter Maydell
Connect the VIRQ and VFIQ lines from the GIC to the CPU; these exist always for both CPU and GIC whether the virtualization extensions are enabled or not, so we can just unconditionally connect them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180821132811.17675-5-peter.maydell@linaro.org
2018-08-24hw/arm/vexpress: Connect VIRQ and VFIQPeter Maydell
Connect the VIRQ and VFIQ lines from the GIC to the CPU; these exist always for both CPU and GIC whether the virtualization extensions are enabled or not, so we can just unconditionally connect them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180821132811.17675-4-peter.maydell@linaro.org
2018-08-23fix "Missing break in switch" coverity reportsPaolo Bonzini
Many of these are marked as "intentional/fix required" because they just need adding a fall through comment. This is exactly what this patch does, except for target/mips/translate.c where it is easier to duplicate the code, and hw/audio/sb16.c where I consulted the DOSBox sources and decide to just remove the LOG_UNIMP before the fallthrough. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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