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path: root/accel/tcg/cputlb.c
AgeCommit message (Expand)Author
2019-01-28cputlb: Remove static tlb sizingRichard Henderson
2019-01-28tcg: introduce dynamic TLB sizingEmilio G. Cota
2019-01-28cputlb: do not evict empty entries to the vtlbEmilio G. Cota
2018-10-31cputlb: Remove tlb_c.pending_flushesRichard Henderson
2018-10-31cputlb: Filter flushes on already clean tlbsRichard Henderson
2018-10-31cputlb: Count "partial" and "elided" tlb flushesRichard Henderson
2018-10-31cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidxRichard Henderson
2018-10-31cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_workRichard Henderson
2018-10-31cputlb: Move env->vtlb_index to env->tlb_d.vindexRichard Henderson
2018-10-31cputlb: Split large page tracking per mmu_idxRichard Henderson
2018-10-31cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flushRichard Henderson
2018-10-31cputlb: Remove tcg_enabled hack from tlb_flush_nocheckRichard Henderson
2018-10-31cputlb: Move tlb_lock to CPUTLBCommonRichard Henderson
2018-10-18cputlb: read CPUTLBEntry.addr_write atomicallyEmilio G. Cota
2018-10-18tcg: Split CONFIG_ATOMIC128Richard Henderson
2018-10-18tcg: Add tlb_index and tlb_entry helpersRichard Henderson
2018-10-18cputlb: serialize tlb updates with env->tlb_lockEmilio G. Cota
2018-10-18cputlb: fix assert_cpu_is_self macroEmilio G. Cota
2018-10-18exec: introduce tlb_initEmilio G. Cota
2018-08-14accel/tcg: Check whether TLB entry is RAM consistently with how we set it upPeter Maydell
2018-08-14accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code()Peter Maydell
2018-08-14accel/tcg: Pass read access type through to io_readx()Peter Maydell
2018-07-16accel/tcg: Assert that tlb fill gave us a valid TLB entryPeter Maydell
2018-07-16accel/tcg: Use correct test when looking in victim TLB for codePeter Maydell
2018-07-02accel/tcg: Avoid caching overwritten tlb entriesRichard Henderson
2018-07-02accel/tcg: Don't treat invalid TLB entries as needing recheckPeter Maydell
2018-07-02accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()Peter Maydell
2018-07-02tcg: Define and use new tlb_hit() and tlb_hit_page() functionsPeter Maydell
2018-06-26tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZEPeter Maydell
2018-06-15cputlb: remove tb_lock from tlb_flush functionsEmilio G. Cota
2018-06-15exec.c: Handle IOMMUs in address_space_translate_for_iotlb()Peter Maydell
2018-06-15cputlb: Pass cpu_transaction_failed() the correct physaddrPeter Maydell
2018-06-15cpu-defs.h: Document CPUIOTLBEntry 'addr' fieldPeter Maydell
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier
2017-11-21accel/tcg: Handle atomic accesses to notdirty memory correctlyPeter Maydell
2017-11-15tcg: Record code_gen_buffer address for user-only memory helpersRichard Henderson
2017-10-20accel/tcg: allow to invalidate a write TLB entry immediatelyDavid Hildenbrand
2017-10-10cputlb: bring back tlb_flush_count under !TLB_DEBUGEmilio G. Cota
2017-09-25accel/tcg/cputlb: avoid recursive BQL (fixes #1706296)Alex Bennée
2017-09-04cputlb: Support generating CPU exceptions on memory transaction failuresPeter Maydell
2017-06-30tcg: consistently access cpu->tb_jmp_cache atomicallyEmilio G. Cota
2017-06-27exec: allow to get a pointer for some mmio memory regionKONRAD Frederic
2017-06-27cputlb: fix the way get_page_addr_code fills the tlbKONRAD Frederic
2017-06-27cputlb: move get_page_addr_codeKONRAD Frederic
2017-06-27cputlb: cleanup get_page_addr_code to use VICTIM_TLB_HITKONRAD Frederic
2017-06-15tcg: move tcg related files into accel/tcg/ subdirectoryYang Zhong
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