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2016-03-01qapi: rename input buttonsGerd Hoffmann
All lowercase, use-dash instead of CamelCase. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-03-01qapi: switch x-input-send-event from console to device+headGerd Hoffmann
Use display device qdev id and head number instead of console index to specify the QemuConsole. This makes things consistent with input devices (for input routing) and vnc server configuration, which both use display and head too. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2016-03-01console: add & use qemu_console_lookup_by_device_nameGerd Hoffmann
We have two places needing this, and a third one will come shortly. So factor things out into a helper function to reduce code duplication. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2016-02-29Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20160229-1' into ↵Peter Maydell
staging usb: redirect bugfix, MAINTAINERS update. # gpg: Signature made Mon 29 Feb 2016 11:09:54 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-usb-20160229-1: usb-redirect: Avoid double free of data MAINTAINERS: Add some missing entries for USB related files Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-29Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20160229-1' into ↵Peter Maydell
staging ui: spice dmabuf fix, MAINTAINERS updates. # gpg: Signature made Mon 29 Feb 2016 10:41:15 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-ui-20160229-1: MAINTAINERS: Add an entry for the include/ui/ folder MAINTAINERS: Add spice-display.h to the SPICE section spice/gl: Enable dmabuf only for spice >= 0.13.1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-29Merge remote-tracking branch 'remotes/kraxel/tags/pull-fw-cfg-20160226-1' ↵Peter Maydell
into staging fw_cfg: unbreak migration compatibility for 2.4 and earlier machines # gpg: Signature made Fri 26 Feb 2016 09:45:50 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-fw-cfg-20160226-1: fw_cfg: unbreak migration compatibility for 2.4 and earlier machines Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-29Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160229' ↵Peter Maydell
into staging ppc patch queue for 2016-02-29 Some more accumulated patches for target-ppc, pseries machine type and related devices to fit in before the qemu-2.6 soft freeze. * Mostly bugfixes and small cleanups for spapr and Mac platforms # gpg: Signature made Mon 29 Feb 2016 06:56:34 GMT using RSA key ID 20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.6-20160229: xics: report errors with the QEMU Error API migration: allow machine to enforce configuration section migration spapr: skip configuration section during migration of older machines dbdma: warn when using unassigned channel spapr: disable vmdesc submission for old machines spapr_pci: fix irq leak in RTAS ibm,change-msi spapr_pci: kill useless variable in rtas_ibm_change_msi() spapr_rng: disable hotpluggability Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-29usb-redirect: Avoid double free of dataFam Zheng
If dropping packets, data is freed, the caller's loop should not continue. Reported by ccc-analyzer. Signed-off-by: Fam Zheng <famz@redhat.com> Message-id: 1456301288-1592-1-git-send-email-famz@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-02-29MAINTAINERS: Add some missing entries for USB related filesThomas Huth
USB-related docs and include files should go into the USB section of the MAINTAINERS file. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1456392967-20274-2-git-send-email-thuth@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-02-29MAINTAINERS: Add an entry for the include/ui/ folderThomas Huth
The ui/ folder is listed in the "Graphics" section, so I think the "include/ui/" folder should be listed there, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1456392967-20274-4-git-send-email-thuth@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-02-29MAINTAINERS: Add spice-display.h to the SPICE sectionThomas Huth
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1456392967-20274-3-git-send-email-thuth@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-02-29spice/gl: Enable dmabuf only for spice >= 0.13.1Michal Privoznik
After 474114b7 the dmabuf feature is enabled whenever spice greater than or equal to spice 0.13.0 is found. This is because two new functions are required: spice_qxl_gl_scanout and spice_qxl_gl_draw_async. These were, however, introduce in 0.13.1 release. Well, technically they haven't been released yet, but for sure they are not going to be part of 0.13.0 release (for the ABI stability sake). Signed-off-by: Michal Privoznik <mprivozn@redhat.com> Message-id: 1a724e97cb587624d6f6009c15395496bccfa32b.1456317738.git.mprivozn@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-02-28xics: report errors with the QEMU Error APIGreg Kurz
Using the return value to report errors is error prone: - xics_alloc() returns -1 on error but spapr_vio_busdev_realize() errors on 0 - xics_alloc_block() returns the unclear value of ics->offset - 1 on error but both rtas_ibm_change_msi() and spapr_phb_realize() error on 0 This patch adds an errp argument to xics_alloc() and xics_alloc_block() to report errors. The return value of these functions is a valid IRQ number if errp is NULL. It is undefined otherwise. The corresponding error traces get promotted to error messages. Note that the "can't allocate IRQ" error message in spapr_vio_busdev_realize() also moves to xics_alloc(). Similar error message consolidation isn't really applicable to xics_alloc_block() because callers have extra context (device config address, MSI or MSIX). This fixes the issues mentioned above. Based on previous work from Brian W. Hart. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-02-28migration: allow machine to enforce configuration section migrationGreg Kurz
Migration of pseries-2.3 doesn't have configuration section. Unfortunately, QEMU 2.4/2.4.1/2.5 are buggy and always stream and expect the configuration section, and break migration both ways. This patch introduces a property which allows to enforce a configuration section for machines who don't have one. It can be set at startup: -machine enforce-config-section=on or later from the QEMU monitor: qom-set /machine enforce-config-section on It is up to the tooling to set or unset this property according to the version of the QEMU at the other end of the pipe. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-02-28spapr: skip configuration section during migration of older machinesGreg Kurz
Since QEMU 2.4, we have a configuration section in the migration stream. This must be skipped for older machines, like it is already done for x86. This patch fixes the migration of pseries-2.3 from/to QEMU 2.3, but it breaks migration of the same machine from/to QEMU 2.4/2.4.1/2.5. We do that anyway because QEMU 2.3 is likely to be more widely deployed than newer QEMU versions. Fixes: 61964c23e5ddd5a33f15699e45ce126f879e3e33 Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-02-28dbdma: warn when using unassigned channelHervé Poussineau
With this, it's easier to know if a guest uses an invalid and/or unimplemented DMA channel. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-02-28spapr: disable vmdesc submission for old machinesGreg Kurz
Since QEMU 2.3, we have a vmdesc section in the migration stream. This section is not mandatory but when migrating a pseries-2.2 machine from QEMU 2.2, you get a warning at the destination: qemu-system-ppc64: Expected vmdescription section, but got 0 The warning goes away if we decide to skip vmdesc as well for older pseries, like it is already done for pc's. This can only be observed with -cpu POWER7 because POWER8 cannot migrate from QEMU 2.2 to 2.3 (insns_flags2 mismatch). Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-02-28spapr_pci: fix irq leak in RTAS ibm,change-msiGreg Kurz
This RTAS call is used to request new interrupts or to free all interrupts. If the driver has already allocated interrupts and asks again for a non-null number of irqs, then the rtas_ibm_change_msi() function will silently leak the previous interrupts. It happens because xics_free() is only called when the driver releases all interrupts (!req_num case). Note that the previously allocated spapr_pci_msi is not leaked because the GHashTable is created with destroy functions and g_hash_table_insert() hence frees the old value. This patch makes sure any previously allocated MSIs are released when a new allocation succeeds. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-02-28spapr_pci: kill useless variable in rtas_ibm_change_msi()Greg Kurz
The num local variable is initialized to zero and has no writer. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-02-28spapr_rng: disable hotpluggabilityGreg Kurz
It is currently possible to hotplug a spapr_rng device but QEMU crashes when we try to hot unplug: ERROR:hw/core/qdev.c:295:qdev_unplug: assertion failed: (hotplug_ctrl) Aborted This happens because spapr_rng isn't plugged to any bus and sPAPR does not provide hotplug support for it: qdev_get_hotplug_handler() hence return NULL and we hit the assertion. And anyway, it doesn't make much sense to unplug this device since hcalls cannot be unregistered. Even the idea of hotplugging a RNG device instead of declaring it on the QEMU command line looks weird. This patch simply disables hotpluggability for the spapr-rng class. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-02-26Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20160226' into staging target-arm queue: * Clean up handling of bad mode switches writing to CPSR, and implement the ARMv8 requirement that they set PSTATE.IL * Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps on perf monitor register accesses * Don't implement stellaris-pl061-only registers on generic-pl061 * Fix SD card handling for raspi * Add missing include files to MAINTAINERS * Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW * Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF # gpg: Signature made Fri 26 Feb 2016 15:19:07 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160226: target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW sdhci: add quirk property for card insert interrupt status on Raspberry Pi sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts" MAINTAINERS: Add some missing ARM related header files raspi: fix SD card with recent sdhci changes ARM: PL061: Checking register r/w accesses to reserved area target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps target-arm: Fix handling of SDCR for 32-bit code target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 target-arm: Make mode switches from Hyp via CPS and MRS illegal target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL target-arm: Forbid mode switch to Mon from Secure EL1 target-arm: Add Hyp mode checks to bad_mode_switch() target-arm: Add comment about not implementing NSACR.RFR target-arm: In cpsr_write() ignore mode switches from User mode linux-user: Use restrictive mask when calling cpsr_write() target-arm: Raw CPSR writes should skip checks and bank switching target-arm: Add write_type argument to cpsr_write() target-arm: Give CPSR setting on 32-bit exception return its own helper Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26Merge remote-tracking branch ↵Peter Maydell
'remotes/amit-migration/tags/migration-for-2.6-5' into staging migration pull - fix a qcow2 assert - fix for older distros (CentOS 5) - documentation for vmstate flags - minor code rearrangement # gpg: Signature made Fri 26 Feb 2016 15:15:15 GMT using RSA key ID 854083B6 # gpg: Good signature from "Amit Shah <amit@amitshah.net>" # gpg: aka "Amit Shah <amit@kernel.org>" # gpg: aka "Amit Shah <amitshah@gmx.net>" * remotes/amit-migration/tags/migration-for-2.6-5: migration (postcopy): move bdrv_invalidate_cache_all of of coroutine context migration (ordinary): move bdrv_invalidate_cache_all of of coroutine context migration/vmstate: document VMStateFlags MAINTAINERS: Add docs/migration.txt to the "Migration" section migration/postcopy-ram: Guard use of sys/eventfd.h with CONFIG_EVENTFD migration: reorder code to make it symmetric Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26migration (postcopy): move bdrv_invalidate_cache_all of of coroutine contextDenis V. Lunev
There is a possibility to hit an assert in qcow2_get_specific_info that s->qcow_version is undefined. This happens when VM in starting from suspended state, i.e. it processes incoming migration, and in the same time 'info block' is called. The problem is that qcow2_invalidate_cache() closes the image and memset()s BDRVQcowState in the middle. The patch moves processing of bdrv_invalidate_cache_all out of coroutine context for postcopy migration to avoid that. This function is called with the following stack: process_incoming_migration_co qemu_loadvm_state qemu_loadvm_state_main loadvm_process_command loadvm_postcopy_handle_run Signed-off-by: Denis V. Lunev <den@openvz.org> Tested-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Juan Quintela <quintela@redhat.com> CC: Amit Shah <amit.shah@redhat.com> Message-Id: <1456304019-10507-3-git-send-email-den@openvz.org> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-02-26migration (ordinary): move bdrv_invalidate_cache_all of of coroutine contextDenis V. Lunev
There is a possibility to hit an assert in qcow2_get_specific_info that s->qcow_version is undefined. This happens when VM in starting from suspended state, i.e. it processes incoming migration, and in the same time 'info block' is called. The problem is that qcow2_invalidate_cache() closes the image and memset()s BDRVQcowState in the middle. The patch moves processing of bdrv_invalidate_cache_all out of coroutine context for standard migration to avoid that. Signed-off-by: Denis V. Lunev <den@openvz.org> Reviewed-by: Fam Zheng <famz@redhat.com> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Juan Quintela <quintela@redhat.com> CC: Amit Shah <amit.shah@redhat.com> Message-Id: <1456304019-10507-2-git-send-email-den@openvz.org> [Amit: Fix a use-after-free bug] Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-02-26target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFPeter Maydell
The v8 ARM ARM defines that unused spaces in the ID_AA64* system register ranges are Reserved and must RAZ, rather than being UNDEF. Implement this. In particular, ARM v8.2 adds a new feature register ID_AA64MMFR2, and newer versions of the Linux kernel will attempt to read this, which causes them not to boot up on versions of QEMU missing this fix. Since the encoding .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6 is actually defined in ARMv8 (as ID_MMFR4), we give it an entry in the ARMCPU struct so CPUs can override it, though since none do this too will just RAZ. Cc: qemu-stable@nongnu.org Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455890863-11203-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org>
2016-02-26target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAWEdgar E. Iglesias
Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW due to the register not having any underlying state. This fixes an issue with booting KVM enabled kernels when EL2 is on. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1456490739-19343-1-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26sdhci: add quirk property for card insert interrupt status on Raspberry PiAndrew Baumann
This quirk is a workaround for the following hardware behaviour, on which UEFI (specifically, the bootloader for Windows on Pi2) depends: 1. at boot with an SD card present, the interrupt status/enable registers are initially zero 2. upon enabling it in the interrupt enable register, the card insert bit in the interrupt status register is immediately set 3. after a subsequent controller reset, the card insert interrupt does not fire, even if enabled in the interrupt enable register Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456436130-7048-3-git-send-email-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26sdhci: Revert "add optional quirk property to disable card insertion/removal ↵Andrew Baumann
interrupts" This reverts commit 723697551a7e926abe7d3c7f2966012b8075143d. This change was poorly tested on my part. It squelched card insertion interrupts on reset, but that was not necessary because sdhci_reset() clears all the registers (via the call to memset), so the subsequent sdhci_insert_eject_cb() call never sees the card insert interrupt enabled. However, not calling the insert_eject_cb results in prnsts remaining 0, when it actually needs to be updated to indicate card presence and R/O status. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456436130-7048-2-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26MAINTAINERS: Add some missing ARM related header filesThomas Huth
Some header files in the include/hw/arm/ directory can be assigned to entries in the MAINTAINERS file. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1456399324-24259-1-git-send-email-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26raspi: fix SD card with recent sdhci changesAndrew Baumann
Recent changes to sdhci broke SD on raspi. This change mirrors the logic to create the SD card device at the board level. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456351128-5560-1-git-send-email-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26ARM: PL061: Checking register r/w accesses to reserved areaWei Huang
pl061.c emulates two GPIO devices, ARM PL061 and TI Stellaris, which share the same read/write functions (pl061_read and pl061_write). However PL061 and Stellaris have different GPIO register definitions and pl061_read()/pl061_write() doesn't check it. This patch enforces checking on offset, preventing R/W into the reserved memory area. Signed-off-by: Wei Huang <wei@redhat.com> Message-id: 1455814580-17699-1-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM trapsPeter Maydell
Implement the performance monitor register traps controlled by MDCR_EL3.TPM and MDCR_EL2.TPM. Most of the performance registers already have an access function to deal with the user-enable bit, and the TPM checks can be added there. We also need a new access function which only implements the TPM checks for use by the few not-EL0-accessible registers and by PMUSERENR_EL0 (which is always EL0-readable). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455892784-11328-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
2016-02-26target-arm: Fix handling of SDCR for 32-bit codePeter Maydell
Fix two issues with our implementation of the SDCR: * it is only present from ARMv8 onwards * it does not contain several of the trap bits present in its 64-bit counterpart the MDCR_EL3 Put the register description in the right place so that it does not get enabled for ARMv7 and earlier, and give it a write function so that we can mask out the bits which should not be allowed to have an effect if EL3 is 32-bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455892784-11328-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
2016-02-26target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1Peter Maydell
If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to NonSecure PL1 modes are illegal mode changes. Implement this check in bad_mode_switch(). (We don't currently implement HCR.TGE, but this is the only missing check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the rest of the HCR.TGE checks can be added later as necessary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-12-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Make mode switches from Hyp via CPS and MRS illegalPeter Maydell
Mode switches from Hyp to any other mode via the CPS and MRS instructions are illegal mode switches (though obviously switching via exception return is valid). Add this check to bad_mode_switch(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-11-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: In v8, make illegal AArch32 mode changes set PSTATE.ILPeter Maydell
In v8, the illegal mode changes which are UNPREDICTABLE in v7 are given architected behaviour: * the mode field is unchanged * PSTATE.IL is set (so any subsequent instructions will UNDEF) * any other CPSR fields are written to as normal This is pretty much the same behaviour we picked for our UNPREDICTABLE handling, with the exception that for v8 we need to set the IL bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-10-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Forbid mode switch to Mon from Secure EL1Peter Maydell
In v8 trying to switch mode to Mon from Secure EL1 is an illegal mode switch. (In v7 this is impossible as all secure modes except User are at EL3.) We can handle this case by making a switch to Mon valid only if the current EL is 3, which then gives the correct answer whether EL3 is AArch32 or AArch64. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-9-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell
We don't actually support Hyp mode yet, but add the correct checks for it to the bad_mode_switch() function for completeness. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-8-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Add comment about not implementing NSACR.RFRPeter Maydell
QEMU doesn't implement the NSACR.RFR bit, which is a permitted IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8. Add a comment to bad_mode_switch() to note that this is why FIQ is always a valid mode regardless of the CPU's Secure state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-7-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell
The only case where we can attempt a cpsr_write() mode switch from User is from the gdbstub; all other cases are handled in the calling code (notably translate.c). Architecturally attempts to alter the mode bits from user mode are simply ignored (and not treated as a bad mode switch, which in v8 sets CPSR.IL). Make mode switches from User ignored in cpsr_write() as well, for consistency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-6-git-send-email-peter.maydell@linaro.org
2016-02-26linux-user: Use restrictive mask when calling cpsr_write()Peter Maydell
When linux-user code is calling cpsr_write(), use a restrictive mask to ensure we are limiting the set of CPSR bits we update. In particular, don't allow the mode bits to be changed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-5-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell
Raw CPSR writes should skip the architectural checks for whether we're allowed to set the A or F bits and should also not do the switching of register banks if the mode changes. Handle this inside cpsr_write(), which allows us to drop the "manually set the mode bits to avoid the bank switch" code from all the callsites which are using CPSRWriteRaw. This fixes a bug in 32-bit KVM handling where we had forgotten the "manually set the mode bits" part and could thus potentially trash the register state if the mode from the last exit to userspace differed from the mode on this exit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-4-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Add write_type argument to cpsr_write()Peter Maydell
Add an argument to cpsr_write() to indicate what kind of CPSR write is being requested, since the exact behaviour should differ for the different cases. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-3-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell
The rules for setting the CPSR on a 32-bit exception return are subtly different from those for setting the CPSR via an instruction like MSR or CPS. (In particular, in Hyp mode changing the mode bits is not valid via MSR or CPS.) Split the exception-return case into its own helper for setting CPSR, so we can eventually handle them differently in the helper function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-2-git-send-email-peter.maydell@linaro.org
2016-02-26migration/vmstate: document VMStateFlagsSascha Silbe
The VMState API is rather sparsely documented. Start by describing the meaning of all VMStateFlags. Reviewed-by: Amit Shah <amit.shah@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Sascha Silbe <silbe@linux.vnet.ibm.com> Message-Id: <1456474693-11662-1-git-send-email-silbe@linux.vnet.ibm.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-02-26MAINTAINERS: Add docs/migration.txt to the "Migration" sectionThomas Huth
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456393669-20678-1-git-send-email-thuth@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-02-26Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160226' into stagingPeter Maydell
MIPS patches 2016-02-26 Changes: * support for FPU and MSA in KVM guest * support for R6 Virtual Processors # gpg: Signature made Fri 26 Feb 2016 11:07:37 GMT using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" * remotes/lalrae/tags/mips-20160226: target-mips: implement R6 multi-threading mips/kvm: Support MSA in MIPS KVM guests mips/kvm: Support FPU in MIPS KVM guests mips/kvm: Support signed 64-bit KVM registers mips/kvm: Support unsigned KVM registers mips/kvm: Implement Config CP0 registers mips/kvm: Implement PRid CP0 register mips/kvm: Remove a couple of noisy DPRINTFs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-signed' ↵Peter Maydell
into staging Update OpenBIOS images # gpg: Signature made Fri 26 Feb 2016 10:45:04 GMT using RSA key ID AE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" * remotes/mcayland/tags/qemu-openbios-signed: Update OpenBIOS images Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26Update OpenBIOS imagesMark Cave-Ayland
Update OpenBIOS images to SVN r1391 built from submodule. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2016-02-26migration/postcopy-ram: Guard use of sys/eventfd.h with CONFIG_EVENTFDMatthew Fortune
sys/eventfd.h was being guarded only by a check for linux but does not exist on older distributions like CentOS 5. Move the include into the code that uses it and add an appropriate guard. Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <6D39441BF12EF246A7ABCE6654B023536BB85DEB@hhmail02.hh.imgtec.org> Signed-off-by: Amit Shah <amit.shah@redhat.com>
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