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2018-09-17target/xtensa: fix FPU2000 bugsMax Filippov
- FPU2000 defines rfr and wfr opcodes, not rfr.s and wfr.s; - movcond.s uses incorrect operand in tcg_gen_movcond: in case the condition is not satisfied it must not change its argument 0. Fixes: c04e1692e3aa ("target/xtensa: extract FPU2000 opcode translators") Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17tests/tcg/xtensa: add test for failed memory transactionsMax Filippov
Failed memory transactions should raise exceptions 14 (for fetch) or 15 (for load/store) with XEA2. Memory accesses that result in TLB miss followed by an attempt to load PTE from physical memory which fails should raise InstTLBMiss or LoadStoreTLBMiss with XEA2. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17target/xtensa: convert to do_transaction_failedMax Filippov
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-19target/xtensa: add test_kc705_be coreMax Filippov
This is big-endian core with HiFi2 instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-19target/xtensa: clean up gdbstub register handlingMax Filippov
- move register counting to xtensa/gdbstub.c - add symbolic names for register types and flags from GDB and use them in register counting and access functions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-19target/xtensa: fix gdbstub register countsMax Filippov
This fixes communication with gdb in the presence of type-5 (TIE state mapped on user registers) and type-7 (special case of masked registers) registers in the xtensa core config. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-17Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' ↵Peter Maydell
into staging x86 queue, 2018-08-16 Bug fix: * Some guests may crash when using "-cpu host" due to TOPOEXT, disable it by default Features: * PV_SEND_IPI feature bit * Icelake-{Server,Client} CPU models * New CPUID feature bits: PV_SEND_IPI, WBNOINVD, PCONFIG, ARCH_CAPABILITIES Documentation: * docs/qemu-cpu-models.texi # gpg: Signature made Fri 17 Aug 2018 02:33:09 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Disable TOPOEXT by default on "-cpu host" target-i386: adds PV_SEND_IPI CPUID feature bit i386: Add new CPU model Icelake-{Server,Client} i386: Add CPUID bit for WBNOINVD i386: Add CPUID bit for PCONFIG i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES docs: add guidance on configuring CPU models for x86 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-2018' ↵Peter Maydell
into staging MIPS queue Aug 16, 2018 # gpg: Signature made Thu 16 Aug 2018 18:19:36 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-aug-2018: qemu-doc: Amend MIPS-related items linux-user: Add preprocessor availability control to some syscalls linux-user: Update MIPS syscall numbers up to kernel 4.18 headers elf: Add ELF flags for MIPS machine variants elf: Remove duplicate preprocessor constant definition target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 target/mips: Don't update BadVAddr register in Debug Mode target/mips: Implement CP0 Config1.WR bit functionality target/mips: Add CP0 BadInstrX register target/mips: Update some CP0 registers bit definitions target/mips: Fix two instances of shadow variables target/mips: Mark switch fallthroughs with interpretable comments target/mips: Avoid case statements formulated by ranges - part 2 target/mips: Avoid case statements formulated by ranges - part 1 MAINTAINERS: Update target/mips maintainer's email addresses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16qemu-doc: Amend MIPS-related itemsAleksandar Markovic
Amend MIPS-related items in qemu-doc.texi Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16linux-user: Add preprocessor availability control to some syscallsAleksandar Rikalo
Add ability to target platforms to individually include user-mode support for system calls from "stat" group of system calls. This change is related to new nanoMIPS platform in the sense that it supports a different set of "stat" system calls than any other target. nanoMIPS does not support structures stat and stat64 at all. Also, support for certain number of other system calls is dropped in nanoMIPS (those are most of the time obsoleted system calls). Without this patch, build for nanoMIPS would fail. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16linux-user: Update MIPS syscall numbers up to kernel 4.18 headersAleksandar Markovic
Synchronize content of linux-user/mips/syscall_nr.h and linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers. This adds 9 new syscall numbers, the last being NR_io_pgetevents. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16elf: Add ELF flags for MIPS machine variantsAleksandar Markovic
Add MIPS machine variants ELF flags so that the emulation behavior can be adjusted if needed. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16elf: Remove duplicate preprocessor constant definitionAleksandar Markovic
Remove duplicate preprocessor constant definition for EF_MIPS_ARCH. The duplicate was introduced in commit 45506bdd. It placed the constant EF_MIPS_ARCH in a better place, however it did not remove the original. This patch removes the original occurrence. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only, and placing ELPA flag checks before switch statement were technically correct. However, after adding handling more registers, these checks should be moved to act only in cases of handling EntryLo0 and EntryLo1. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Don't update BadVAddr register in Debug ModeYongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is set. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Implement CP0 Config1.WR bit functionalityStefan Markovic
Add testing Config1.WR bit into watch exception handling logic. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Add CP0 BadInstrX registerStefan Markovic
Add CP0 BadInstrX register. This register will be used in nanoMIPS. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Update some CP0 registers bit definitionsAleksandar Markovic
Update CP0 registers Config0, Config1, Config2, Config3, Config4, and Config5 bit definitions. Some of these bits will be utilized by upcoming nanoMIPS changes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Fix two instances of shadow variablesAleksandar Markovic
Fix two instances of shadow variables. This cleans up entire file translate.c from shadow variables. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Mark switch fallthroughs with interpretable commentsAleksandar Markovic
Mark switch fallthroughs with comments, in cases fallthroughs are intentional. The comments "/* fall through */" are interpreted by compilers and other tools, and they will not issue warnings in such cases. For gcc, the warning is turnend on by -Wimplicit-fallthrough. With this patch, there will be no such warnings in target/mips directory. If such warning appears in future, it should be checked if it is intentional, and, if yes, marked with a comment similar to those from this patch. The comment must be just before next "case", otherwise gcc won't understand it. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Avoid case statements formulated by ranges - part 2Aleksandar Rikalo
Remove "range style" case statements to make code analysis easier. This patch handles cases when the values in the range in question were not properly defined. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Avoid case statements formulated by ranges - part 1Aleksandar Markovic
Remove "range style" case statements to make code analysis easier. This is needed also for some upcoming nanoMIPS-related refactorings. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16MAINTAINERS: Update target/mips maintainer's email addressesAleksandar Markovic
Update email addresses of Aleksandar Markovic and Paul Burton in the MAINTAINERS file. Also, add corresponding items in the .mailmap file. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16i386: Disable TOPOEXT by default on "-cpu host"Eduardo Habkost
Enabling TOPOEXT is always allowed, but it can't be enabled blindly by "-cpu host" because it may make guests crash if the rest of the cache topology information isn't provided or isn't consistent. This addresses the bug reported at: https://bugzilla.redhat.com/show_bug.cgi?id=1613277 Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180809221852.15285-1-ehabkost@redhat.com> Tested-by: Richard W.M. Jones <rjones@redhat.com> Reviewed-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16target-i386: adds PV_SEND_IPI CPUID feature bitWanpeng Li
Adds PV_SEND_IPI CPUID feature bit. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Message-Id: <1530526971-1812-1-git-send-email-wanpengli@tencent.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add new CPU model Icelake-{Server,Client}Robert Hoo
New CPU models mostly inherit features from ancestor Skylake, while addin new features: UMIP, New Instructions ( PCONIFIG (server only), WBNOINVD, AVX512_VBMI2, GFNI, AVX512_VNNI, VPCLMULQDQ, VAES, AVX512_BITALG), Intel PT and 5-level paging (Server only). As well as IA32_PRED_CMD, SSBD support for speculative execution side channel mitigations. Note: For 5-level paging, Guest physical address width can be configured, with parameter "phys-bits". Unless explicitly specified, we still use its default value, even for Icelake-Server cpu model. At present, hold on expose IA32_ARCH_CAPABILITIES to guest, as 1) This MSR actually presents more than 1 'feature', maintainers are considering expanding current features presentation of only CPUIDs to MSR bits; 2) a reasonable default value for MSR_IA32_ARCH_CAPABILITIES needs to settled first. These 2 are actully beyond Icelake CPU model itself but fundamental. So split these work apart and do it later. https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-6-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add CPUID bit for WBNOINVDRobert Hoo
WBNOINVD: Write back and do not invalidate cache, enumerated by CPUID.(EAX=80000008H, ECX=0):EBX[bit 9]. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-5-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add CPUID bit for PCONFIGRobert Hoo
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0): EDX[bit18]. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-4-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSRRobert Hoo
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's comment. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIESRobert Hoo
IA32_PRED_CMD MSR gives software a way to issue commands that affect the state of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26]. IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29]. https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16docs: add guidance on configuring CPU models for x86Daniel P. Berrangé
With the recent set of CPU hardware vulnerabilities on x86, it is increasingly difficult to understand which CPU configurations are good to use and what flaws they might be vulnerable to. This doc attempts to help management applications and administrators in picking sensible CPU configuration on x86 hosts. It outlines which of the named CPU models are good choices, and describes which extra CPU flags should be enabled to allow the guest to mitigate hardware flaws. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20180627160103.13634-1-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180816' into staging target-arm queue: * Fixes for various bugs in SVE instructions * Add model of Freescale i.MX6 UltraLite 14x14 EVK Board * hw/arm: make bitbanded IO optional on ARMv7-M * Add model of Cortex-M0 CPU * Add support for loading Intel HEX files to the generic loader * imx_spi: Unset XCH when TX FIFO becomes empty * aspeed_sdmc: fix various bugs * Fix bugs in Arm FP16 instruction support * Fix aa64 FCADD and FCMLA decode * softfloat: Fix missing inexact for floating-point add * hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() # gpg: Signature made Thu 16 Aug 2018 14:33:41 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180816: (30 commits) hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() softfloat: Fix missing inexact for floating-point add target/arm: Fix aa64 FCADD and FCMLA decode target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h target/arm: Ignore float_flag_input_denormal from fp_status_f16 target/arm: Adjust FPCR_MASK for FZ16 aspeed: add a max_ram_size property to the memory controller aspeed_sdmc: Handle ECC training aspeed_sdmc: Init status always idle aspeed_sdmc: Set 'cache initial sequence' always true aspeed_sdmc: Fix saved values aspeed_sdmc: Extend number of valid registers imx_spi: Unset XCH when TX FIFO becomes empty Add QTest testcase for the Intel Hexadecimal loader: Implement .hex file loader loader: add rom transaction API loader: extract rom_free() function target/arm: add "cortex-m0" CPU model hw/arm: make bitbanded IO optional on ARMv7-M ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()Thomas Huth
Now that we've got the common sysbus_init_child_obj() function, we do not need the local init_sysbus_child() anymore. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1534420566-15799-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16softfloat: Fix missing inexact for floating-point addRichard Henderson
For 0x1.0000000000003p+0 + 0x1.ffffffep+14 = 0x1.0001fffp+15 we dropped the sticky bit and so failed to raise inexact. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Fix aa64 FCADD and FCMLA decodeRichard Henderson
These insns require u=1; failed to include that in the switch cases. This probably happened during one of the rebases just before final commit. Fixes: d17b7cdcf4e Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-halfRichard Henderson
We were using the wrong flush-to-zero bit for the non-half input. Fixes: 46d33d1e3c9 Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_hRichard Henderson
This makes float16_muladd correctly use FZ16 not FZ. Fixes: 6ceabaad110 Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Ignore float_flag_input_denormal from fp_status_f16Richard Henderson
When FZ is set, input_denormal exceptions are recognized, but this does not happen with FZ16. The softfloat code has no way to distinguish these bits and will raise such exceptions into fp_status_f16.flags, so ignore them when computing the accumulated flags. Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Adjust FPCR_MASK for FZ16Richard Henderson
When support for FZ16 was added, we failed to include the bit within FPCR_MASK, which means that it could never be set. Continue to zero FZ16 when ARMv8.2-FP16 is not enabled. Fixes: d81ce0ef2c4 Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed: add a max_ram_size property to the memory controllerCédric Le Goater
This will be used to construct a memory region beyond the RAM region to let firmwares scan the address space with load/store to guess how much RAM the SoC has. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-7-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed_sdmc: Handle ECC trainingJoel Stanley
This is required to ensure u-boot SDRAM training completes. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-6-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed_sdmc: Init status always idleJoel Stanley
The ast2500 SDRAM training routine busy waits on the 'init cycle busy state' bit in DDR PHY Control/Status register #1 (MCR60). This ensures the bit always reads zero, and allows training to complete with upstream u-boot on the ast2500-evb. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-5-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed_sdmc: Set 'cache initial sequence' always trueJoel Stanley
The SDRAM training routine sets the 'Enable cache initial' bit, and then waits for the 'cache initial sequence' to be done. Have it always return done, as there is no other side effects that the model needs to implement. This allows the upstream u-boot training to proceed on the ast2500-evb board. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-4-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed_sdmc: Fix saved valuesJoel Stanley
This fixes the intended protection of read-only values in the configuration register. They were being always set to zero by mistake. The read-only fields depend on the configured memory size of the system, so they cannot be fixed at compile time. The most straight forward option was to store them in the state structure. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-3-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed_sdmc: Extend number of valid registersJoel Stanley
The SDMC on the ast2500 has 170 registers. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-2-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16imx_spi: Unset XCH when TX FIFO becomes emptyTrent Piepho
The current emulation will clear the XCH bit when a burst finishes. This is not quite correct. According to the i.MX7d referemce manual, Rev 0.1, §10.1.7.3: This bit [XCH] is cleared automatically when all data in the TXFIFO and the shift register has been shifted out. So XCH should be cleared when the FIFO empties, not on completion of a burst. The FIFO is 64 x 32 bits = 2048 bits, while the max burst size is larger at 4096 bits. So it's possible that the burst is not finished after the TXFIFO empties. Sending a large block (> 2048 bits) with the Linux driver will use a burst that is larger than the TXFIFO. After the TXFIFO has emptied XCH does not become unset, as the burst is not yet finished. What should happen after the TXFIFO empties is the driver will refill it and set XCH. The rising edge of XCH will trigger another transfer to begin. However, since the emulation does not set XCH to 0, there is no rising edge and the next trasfer never begins. Signed-off-by: Trent Piepho <tpiepho@impinj.com> Message-id: 20180731201056.29257-1-tpiepho@impinj.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16Add QTest testcase for the Intel HexadecimalSu Hang
'test.hex' file is a memory test pattern stored in Hexadecimal Object Format. It loads at 0x10000 in RAM and contains values from 0 through 255. The test case verifies that the expected memory test pattern was loaded. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Suggested-by: Steffen Gortz <qemu.ml@steffen-goertz.de> Suggested-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Su Hang <suhang16@mails.ucas.ac.cn> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMM: changed qtest_startf() to qtest_initf() to work with current master after the refactoring in commit 88b988c895e3c2] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16loader: Implement .hex file loaderSu Hang
This patch adds Intel Hexadecimal Object File format support to the generic loader device. The file format specification is available here: http://www.piclist.com/techref/fileext/hex/intel.htm This file format is often used with microcontrollers such as the micro:bit, Arduino, STM32, etc. Users expect to be able to run .hex files directly with without first converting them to ELF. Most micro:bit code is developed in web-based IDEs without direct user access to binutils so it is important for QEMU to handle this file format natively. Signed-off-by: Su Hang <suhang16@mails.ucas.ac.cn> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20180814162739.11814-6-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16loader: add rom transaction APIStefan Hajnoczi
Image file loaders may add a series of roms. If an error occurs partway through loading there is no easy way to drop previously added roms. This patch adds a transaction mechanism that works like this: rom_transaction_begin(); ...call rom_add_*()... rom_transaction_end(ok); If ok is false then roms added in this transaction are dropped. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20180814162739.11814-5-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16loader: extract rom_free() functionStefan Hajnoczi
The next patch will need to free a rom. There is already code to do this in rom_add_file(). Note that rom_add_file() uses: rom = g_malloc0(sizeof(*rom)); ... if (rom->fw_dir) { g_free(rom->fw_dir); g_free(rom->fw_file); } The conditional is unnecessary since g_free(NULL) is a no-op. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180814162739.11814-4-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>